TMC22091 Datasheet, PDF (5/60 Pages) Fairchild Semiconductor – Digital Video Encoders/Layering Engine

PRODUCT SPECIFICATION
TMC22091/TMC22191
Microprocessor Interface
The microprocessor interface employs a 13 line format. The
RESET pin sets all internal state machines to their initialized
conditions, disables the analog outputs, sets the internal
SRESET bit LOW (reset condition), and places the encoder
in a power-down mode. All register and CLUT data are
maintained in power-down mode. If the HRESET bit is set
HIGH, line 1 field 1 is started when RESET goes HIGH, and
SRESET is ignored. If HRESET is LOW, the encoder
remains idle after RESET goes HIGH until Control Register
bit SRESET is set HIGH, which initiates line 1 field 1.
Two address lines are provided and decoded for access to the
internal Control Registers and CLUT. Control Registers and
CLUT are accessed by loading a desired address through the
8-bit D7-0 port, followed by the desired data read or write for
that address. Both the CLUT and the Control Registers are
self-indexing, allowing continuous reads or writes to succes-
sive addresses.
JTAG Test Interface
The TMC22x91 includes a standard 4-line JTAG (IEEE Std
1149.1-1990) test interface port, providing access to all digi-
tal input/output data pins. This is provided to facilitate com-
ponent and board-level testing.
Test/Validation Mode
The TMC22x91 may be configured to produce standard
color bars or a 40 IRE modulated (or unmodulated) video
ramp, independent of any pixel or video data input. Color
bars are useful as an idle system output signal. The test sig-
nals may be used to verify proper operation of the analog
video signal chain.
TMC22090/TMC22190 Compatibility
The TMC22090 and TMC22190 are earlier versions of the
TMC22091 and TMC22191, respectively. They lack the fol-
lowing features of the newer versions:
1. Selectable Setup (to support NTSC EIA-J video output
for Japan)
2. PAL-M format (for South American applications)
3. Extended EH and SL intervals (to support pixel rates
above 15 Mpps)
4. Individual D/A power-down (to reduce total dissipation
when some outputs are not required)
5. Luminance I/O processing (to reduce flicker in graphics
applications)
These features are controlled by registers 0E and 0F, and
enabled by setting Register OE bit 7 to ONE. If an applica-
tion of the TMC22x90 is programmed with this bit set to
ZERO (as recommended in the product documentation) then
the corresponding TMC22x91 will perform identically.
Though the earlier parts continue to be available, it is recom-
mended that the newer devices be used in new designs for
the additional flexibility. Older designs may be readily
converted to the newer versions to take advantage of the
added features and lower cost of the later technology.
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