SPT5510 Datasheet, PDF (4/8 Pages) Fairchild Semiconductor – 16-BIT, 200 MWPS ECL D/A CONVERTER

THEORY OF OPERATION
The SPT5510 is a segmented 16-bit current-output DAC.
The four MSBs, D15–D12, are decoded to fifteen unit cells
(current sinks). The remaining bits (D11–D0) are binary;
bits D9–D0 are derived from an R-2R ladder. All cells are
laser trimmed for maximum accuracy. The block diagram
shows the basic architecture.
All output cells are always on, with the data determining
whether a given cell’s current is routed from I_OUT or I_OUT.
This provides nearly constant power dissipation indepen-
dent of data and clock rate. It also reduces noise transients
on power and ground lines.
The reference loop utilizes an MSB-weighted cell and pro-
vides a gain of about 16 to the output. The on-chip refer-
ence amplifier has very high open-loop gain and is offset
trimmed to provide a very low temperature drift (typically
<10 ppm/°C gain drift).
POWER SUPPLY AND GROUNDING
The SPT5510 requires a single –5.2V power supply. All
supply pins attach to a common on-chip power bus and
should be treated as analog supplies. For best settling per-
formance, each supply pin should be decoupled as shown
in figure 1 – typical interface circuit.
There are three separate on-chip ground busses. DGND
pins should be tied together and connected to system
ground through a ferrite bead. REFGND and OGND pins
should be tied directly to the SPT5510’s ground plane and
connected to system ground through a ferrite bead. It is
critical that REFGND and OGND are very tightly coupled,
as any differential signal (dc offset, noise, etc.) will be
transmitted to the output. Two of the OGND pins can be
disconnected from the ground plane and used as sense
lines for a current-to-voltage converter, as shown in the
OUTPUTS section.
Figure 1 – Typical Interface Circuit
C13 20 pF
C12 10 pF
AVEE
R10 50
Input
Data
1 _D15
2 _D14
3 _D13
4
D12
5
D11
6
D10
7
D9
8
D8
25
D7
26 _D6
27
D5
28
29 ^D4
D3
30
31 ^D2
D1
32 _D0
SPT5510
41
IOUT
Output
IOUT ³⁶
Output
Complementary
FB
C1–C13 — SURFACE MOUNT CERAMIC CHIP
C14–C17 — TANTALUM
R1–R6 — CARBON FILM 1/4 W
R7–R10 — SURFACE MOUNT CERAMIC CHIP
FB — FERRITE BEAD is to be located as closely _AVEE
to the device as possible.
SPT5510
4
9/27/00