CDK8307_1A Datasheet, PDF (1/31 Pages) Cadeka Microcircuits LLC. – 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS

Data Sheet
Amplify the Human Experience
CDK8307
12/13-bit, 20/40/50/65/80MSPS, Eight Channel,
Ultra Low Power ADC with LVDS
FEATURES
n 20/40/50/65/80MSPS max sampling rate
n Low Power Dissipation
– 23mW/channel at 20MSPS
– 35mW/channel at 40MSPS
– 41mW/channel at 50MSPS
– 51mW/channel at 65MSPS
– 59mW/channel at 80MSPS
n 72.2dB SNR at 8MHz F_IN
n 0.5μs startup time from Sleep
n 15μs startup time from Power Down
n Internal reference circuitry requires no
external components
n Internal offset correction
n Reduced power dissipation modes available
– 34mW/channel at 50MSPS
– 71.5dB SNR at 8MHz FIN
n Coarse and fine gain control
n 1.8V supply voltage
n Serial LVDS output
– 12- and 14-bit output available
n Package alternatives
– TQFP-80
– QFN-64
APPLICATIONS
n Medical Imaging
n Wireless Infrastructure
n Test and Measurement
n Instrumentation
General Description
The CDK8307 is a high performance low power octal analog-to-digital
converter (ADC). The ADC employs internal reference circuitry, a serial control
interface and serial LVDS output data, and is based on a proprietary structure.
An integrated PLL multiplies the input sampling clock by a factor of 12 or 14,
according to the LVDS output setting. The multiplied clock is used for data
serialization and data output. Data and frame synchronization output clocks are
supplied for data capture at the receiver.
Various modes and configuration settings can be applied to the ADC through
the serial control interface (SPI). Each channel can be powered down inde-
pendently and data format can be selected through this interface. A full chip
idle mode can be set by a single external pin. Register settings determines the
exact function of this external pin.
The CDK8307 is designed to easily interface with field-programmable gate
arrays (FPGAs) from several vendors.
The very low startup times of the CDK8307 allow significant power reduction
in duty-cycled systems, by utilizing the Sleep Mode or Power Down Mode when
the receive path is idle.
Block Diagram
Serial Control
Interface
IP1
ADC
IN1
IP2
ADC
IN2
•••
IP8
ADC
IN8
Clock
Input
PLL
LVDS
Digital
Gain
LVDS
Digital
Gain
•••
Digital
Gain
LVDS
•••
LVDS
FCLKP
FCLKN
LCLKP
LCLKN
D1N
D1P
D2N
D2P
D8N
D8P
©2009 CADEKA Microcircuits LLC
www.cadeka.com