VFC100 Datasheet, PDF (9/15 Pages) Burr-Brown (TI) – Synchronized VOLTAGE-TO-FREQUENCY CONVERTER

R_{2 2MΩ}
R₁
V_IN
500 Ω
±1% Gain Trim
5 ^CINT
Clock
4 14
10
7
R_IN
6
Clocked
Logic
+15VDC
1 ^0.1µF
+V_CC
Output
One-Shot
+V_L
0.1µF
11
f _OUT
12
R₃ 20kΩ
–V_CC
13
15
R₅
±3.75mV
Offset Trim
R_{4 500Ω 350kΩ}
FIGURE 9. Circuit Diagram for Fine Offset and Gain Trim.
5V
Reference
16
–V_CC
9
8
0.1µF
+15VDC –15VDC
0.03
3
0.015
0.02
2
Nonlinearity
0.01
1
Gain Error
0.01
0.005
0
0
0
0
500k
1M
f_FS – Full Scale Frequency (Hz)
FIGURE 10. Typical Nonlinearity and Gain Error vs Full
Scale Frequency.
–0.005
0
2
4
6
8
10
V_IN (V)
FIGURE 11. Typical Nonlinearity vs V_IN. (f_FS = 0.1MHz)
at higher operating frequency. The VFC100’s gain drift
remains excellent at higher operating frequency, typically
remaining within specifications at f_FS = 1MHz.
Drift of the external clock frequency directly affects the
output frequency, but by using a common clock for the VFC
and counting circuitry, this drift can be cancelled (see
“Counting the Output”).
POWER SUPPLIES AND GROUNDING
Separate analog and digital grounds are provided on the
VFC100 and it is important to separate these grounds to
attain greatest accuracy. Logic sink current flowing in the
f_OUT pin is returned to the digital ground. If this “noisy”
current were allowed to flow in analog ground, errors could
be created. Although analog and digital grounds may even-
tually be connected together at a common point in the
circuitry, separate circuit connections to this common point
can reduce the error voltages created by varying currents
flowing through the ground return impedance. The +5V
V_REF pin is referenced to analog ground.
The power supplies should be well bypassed using capaci-
tors with low impedance at high frequency. A value of 0.1µF
is adequate for most circuit layouts.
The VFC100 is specified for a nominal supply voltage of
±15V. Supply voltages ranging from ±7.5V to ±18V may be
used. Either supply can be up to 28V as long as the total of
both does not exceed 36V. Steps must be taken, however, to
assure that the integrator output does not exceed its linear
range. Although the integrator output is capable of 12V
output swing with 15V power supplies, with 7.5V supplies,
output swing will be limited to approximately 4.5V. In this
case, the comparator input cannot be offset by directly
connecting to the 5V reference output pin. The comparator
input must be connected to a lower voltage point (approxi-
mately 2V). This allows the integrator output to operate
around a lower voltage point, assuring linear operation. This
threshold voltage does not affect the accuracy or drift of the
VFC as long as it is not noisy. It should not be made too
®
9
VFC100