AFE1105 Datasheet, PDF (9/10 Pages) Burr-Brown (TI) – HDSL/MDSL ANALOG FRONT END

DISCUSSION OF
SPECIFICATIONS
UNCANCELLED ECHO
The key measure of transceiver performance is uncancelled
echo. This measurement is made as shown in the diagram of
Figure 4. The AFE is connected to an output circuit includ-
ing a typical 1:2 line transformer. The line is simulated by a
135Ω resistor. Symbol sequences are generated by the tester
and applied both to the AFE and to the input of an adaptive
filter. The output of the adaptive filter is subtracted from the
AFE output to form the uncancelled echo signal. Once the
filter taps have converged, the RMS value of the uncancelled
echo is calculated. Since there is no far-end signal source or
additive line noise, the uncancelled echo contains only noise
and linearity errors generated in the transmitter and receiver.
The data sheet value for uncancelled echo is the ratio of the
RMS uncancelled echo (referred to the receiver input through
the receiver gain) to the nominal transmitted signal (13.5dBm
into 135Ω, or 1.74Vrms). This echo value is measured under
a variety of conditions: with loopback enabled (line input
disconnected); with loopback disabled under all receiver
gain ranges; and with the line shorted (S₁ closed in Figure 4).
LAYOUT
The analog front end of an HDSL system has a number of
conflicting requirements. It must accept and deliver digital
outputs at fairly high rates of speed, phase-lock to a high-
speed digital clock, and convert the line input to a high-
precision (14-bit) digital output. Thus, there are really three
sections of the AFE1105: the digital section, the phase-
locked loop, and the analog section.
The power supply for the digital section of the AFE1105 can
range from 3.3V to 5V. This supply should be decoupled to
digital ground with a ceramic 0.1µF capacitor placed as
close to DGND (pin 12) and DV_DD (pin 13) as possible.
Ideally, both a digital power supply plane and a digital
ground plane should run up to and underneath the digital
pins of the AFE1105 (pins 3 through 26). However, DV_DD
may be supplied by a wide printed circuit board (PCB) trace.
A digital ground plane underneath all digital pins is strongly
recommended.
The phase-locked loop is powered from PV_DD (pin 2) and its
ground is referenced to PGND (pin 1). Note that PV_DD must
be in the 4.75V to 5.25V range. This portion of the AFE1105
should be decoupled with both a 10µF Tantalum capacitor
Transmit
Data
Uncancelled
Echo
txDAT_P
txLINE_P
txLINE_N
rxHYB_P
AFE1105
rxHYB_N
rxLINE_P
rxLINE_N
rxD13 - rxD0 REF_N
576Ω
100pF
0.01µF
1.54kΩ
150Ω
750Ω
576Ω
100pF
750Ω
13Ω
13Ω
0.047µF
2kΩ
2kΩ
0.047µF
0.1µF
2kΩ
2kΩ
0.1µF
1:2 5.6Ω
5.6Ω
135Ω
S₁
FIGURE 4. Uncancelled Echo Test Diagram.
®
9
AFE1105