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ADS7824 Datasheet, PDF (9/16 Pages) Burr-Brown (TI) – 4 Channel, 12-Bit Sampling CMOS A/D Converter
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R/C
BUSY
MODE
t3
t6
Acquire
Parallel Previous
Data Bus High Byte Valid
t9
BYTE
t1
t4
t7
Convert
t12
t11
Hi-Z
Previous High Previous Low
Byte Valid
Byte Valid
t2
t12
t3
t5
t6
t8
Acquire
t10
Not Valid
t12
High Byte
Valid
Low Byte
Valid
t12
t1
Convert
t12
Hi-Z
t9
High Byte
Valid
t12
FIGURE 2. Conversion Timing with Parallel Output (CS LOW).
R/C
CS
BUSY
BYTE
t21
t21
t1
t3
t4
t21
t21
t21
t21
t21
t21
t21
t21
DATA
BUS
Hi-Z State
High Byte Hi-Z State Low Byte
t12
t9
t12
Hi-Z State
t9
FIGURE 3. Using CS to Control Conversion and Read Timing with Parallel Outputs.
CS or R/C(1)
DATACLK
SDATA
Hi-Z
BUSY
t14
t13
1
2
3
t16
t15
MSB Valid
Bit 10 Valid
Bit 9 Valid
t25
(Results from previous conversion.)
t7 + t8
11
12
Bit 1 Valid
LSB Valid
NOTE: (1) If controlling with CS, tie R/C LOW. If controlling with R/C, tie CS LOW.
FIGURE 4. Serial Data Timing Using Internal Data Clock (TAG LOW).
9
Hi-Z
t26
1
2
MSB Valid
Bit 10 Valid
®
ADS7824
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