CS5550 Datasheet, PDF (8/24 Pages) Cirrus Logic – Two-channel, Low-cost A/D Converter

CS5550
SWITCHING CHARACTERISTICS
Parameter
Symbol Min
Typ
Max Unit
Master Clock Frequency Internal Gate Oscillator (Note 7) MCLK
2.5
4.096
5
MHz
Master Clock Duty Cycle
40
-
60
%
CPUCLK Duty Cycle
(Note 8)
40
60
%
Rise Times
(Note 9)
Any Digital Input Except SCLK t_rise
-
SCLK
-
-
1.0
µs
-
100
µs
Any Digital Output
-
50
-
ns
Fall Times
(Note 9)
Any Digital Input Except SCLK t_fall
SCLK
Any Digital Output
-
-
1.0
µs
-
-
100
µs
-
50
-
ns
Start-up
Oscillator Start-Up Time
XTAL = 4.096 MHz (Note 10) t_ost
-
60
-
ms
Serial Port Timing
Serial Clock Frequency
SCLK
-
-
2
MHz
Serial Clock
Pulse Width High
t₁
Pulse Width Low
t₂
200
-
200
-
-
ns
-
ns
SDI Timing
CS Falling to SCLK Rising
t₃
50
-
-
ns
Data Set-up Time Prior to SCLK Rising
t₄
50
-
-
ns
Data Hold Time After SCLK Rising
t₅
100
-
-
ns
SCLK Falling Prior to CS Disable
t₆
100
-
-
ns
SDO Timing
CS Falling to SDI Driving
t₇
-
20
50
ns
SCLK Falling to New Data Bit (hold time)
t₈
-
20
50
ns
CS Rising to SDO Hi-Z
t₉
-
20
50
ns
Notes: 7. Device parameters are specified with a 4.096 MHz clock. If a crystal is used, then XIN frequency must
remain between 2.5 MHz - 5.0 MHz.
8. If external MCLK is used, then its duty cycle must be between 45% and 55% to maintain this spec.
9. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF.
10. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an
external clock source.
8
DS630F1