CS4223 Datasheet, PDF (8/32 Pages) Cirrus Logic – 24-Bit 105 dB Audio Codec with Volume Control

CS4223 CS4224
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE (CS4224)
(T_A = 25° C; VA, VD = 4.75 V - 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VD; C_L = 30 pF)
Parameter
Symbol
Min
Max
Unit
SPI Mode (SPI/I2C = 0)
CCLK Clock Frequency
RST rising edge to CS falling
CCLK edge to CS falling
CS High Time between transmissions
CS falling to CCLK edge
CCLK Low Time
CCLK High Time
CDIN to CCLK rising setup time
CCLK rising to DATA hold time
Rise time of CCLK and CDIN
Fall time of CCLK and CDIN
f_sck
-
(Note 11)
t_srs
41
(Note 12)
t_spi
500
t_csh
1.0
t_css
20
t_scl
66
t_sch
66
t_dsu
40
(Note 13)
t_dh
15
(Note 14)
t_r2
-
(Note 14)
t_f2
-
6
MHz
-
µs
-
ns
-
µs
-
ns
-
ns
-
ns
-
ns
-
ns
100
ns
100
ns
Notes: 11. Not tested but guaranteed by design.
12. t_spi only needed before first falling edge of CS after RST rising edge. t_spi = 0 at all other times.
13. Data must be held for sufficient time to bridge the transition time of CCLK.
14. For F_SCK < 1 MHz.
RST
t _srs
CS
CCLK
CDIN
t _spi tcss
t _scl t _sch
t _r2
t _f2
t _{dsu t dh}
Figure 2. SPI Control Port Timing
t _csh
8
DS290PP3