BUF20820 Datasheet, PDF (8/32 Pages) Burr-Brown (TI) – 18-Channel GAMMA VOLTAGE GENERATOR with Two Programmable VCOM Channels

BUF20820
SBOS330C − DECEMBER 2005 − REVISED OCTOBER 2006
DATA RATES
The two-wire bus operates in one of three speed modes:
D Standard: allows a clock frequency of up to 100kHz;
D Fast: allows a clock frequency of up to 400kHz; and
D High-speed mode (or Hs mode): allows a clock
frequency of up to 3.4MHz.
The BUF20820 is fully compatible with all three modes. No
special action is required to use the device in Standard or
Fast modes, but High-speed mode must be activated. To
activate High-speed mode, send a special address byte of
00001xxx, with SCL = 400kHz, following the START
condition; xxx are bits unique to the Hs-capable master,
which can be any value. This byte is called the Hs master
code. (Note that this is different from normal address
bytes—the low bit does not indicate read/write status.) The
BUF20820 will respond to the High-speed command
regardless of the value of these last three bits. The
BUF20820 will not acknowledge this byte; the
communication protocol prohibits acknowledgement of
the Hs master code. On receiving a master code, the
BUF20820 will switch on its Hs mode filters, and
communicate at up to 3.4MHz. Additional high-speed
transfers may be initiated without resending the Hs mode
byte by generating a repeat START without a STOP. The
BUF20820 will switch out of Hs mode with the next STOP
condition.
GENERAL CALL RESET AND POWER-UP
The BUF20820 responds to a General Call Reset, which
is an address byte of 00h (0000 0000) followed by a data
byte of 06h (0000 0110). The BUF20820 acknowledges
both bytes. Upon receiving a General Call Reset, the
BUF20820 performs a full internal reset, as though it had
been powered off and then on. It always acknowledges the
General Call address byte of 00h (0000 0000), but does
not acknowledge any General Call data bytes other than
06h (0000 0110).
The BUF20820 automatically performs a reset upon
power-up. As part of the reset, the BUF20820 is configured
for all outputs to change to the programmed OTP memory
values, or (V_REFH − V_REFL)/2 if the OTP values have not
been programmed.
The BUF20820 resets all outputs to the OTP memory
values (or to (V_REFH − V_REFL)/2 if the OTP values have not
been programmed) when the device address is sent,
followed by a valid DAC address with bits D7 to D5 set to
‘100’. If these bits are set to ‘010’, only the DAC being
addressed will be reset.
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OUTPUT VOLTAGE
Buffer output values are determined by the reference
voltages (V_REFH and V_REFL) and the decimal value of the
binary input code used to program that buffer. The value is
calculated using Equation 1:
ƪ ƫ V_OUT +
V_REFH * V_REFL
1024
Decimal Value of Code ) V_REFL
(1)
The valid voltage ranges for the reference voltages are:
4V v V_REFH v V_S * 0.2V and 0.2V v V_REFL v V_S * 4V ₍₂₎
The BUF20820 outputs are capable of a full-scale voltage
output change in typically 5µs—no intermediate steps are
required.
OUTPUT LATCH
Updating the DAC register is not the same as updating the
DAC output voltage, because the BUF20820 features a
double-buffered register structure. There are three
methods for latching transferred data from the storage
registers into the DACs to update the DAC output
voltages.
Method 1 requires externally setting the latch pin (LD)
LOW, LD = LOW, which will update each DAC output
voltage whenever its corresponding register is updated.
Method 2 externally sets LD = HIGH to allow all DAC
output voltages to retain their values during data transfer
and until LD = LOW, which will then simultaneously update
the output voltages of all DACs to the new register values.
Use this method to transfer a future data set in advance to
prepare for a very fast output voltage update.
Method 3 uses software control. LD is maintained HIGH,
and all DACs are updated when the master writes a 1 in bit
15 and a 0 in bit 14 of any DAC register. The update will
occur after receiving the 16-bit data for the
currently-written register.
The General Call Reset and the power-up reset will update
the DAC regardless of the state of the latch pin.
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