SHC298 Datasheet, PDF (7/8 Pages) Burr-Brown (TI) – Monolithic SAMPLE/HOLD AMPLIFIER

CHARGE OFFSET
Charge Offset is the offset that results from the charge
coupled through the gate capacitance of the switching FET.
This charge is coupled into the storage capacitor when the
FET is switched to the “hold” mode.
OPERATING INSTRUCTIONS
EXTERNAL CAPACITOR SELECTION
Capacitors with high insulation resistance and low dielectric
absorption, such as Teflon^®, polystyrene or polypropylene
units, should be used as storage elements (polystyrene should
not be used above +85°C). Care should be taken in the
printed circuit layout to minimize AC and DC leakage
currents from the capacitor to reduce charge offset and
droop errors.
The value of the external capacitor determines the droop,
charge offset and acquisition time of the Sample/Hold. Both
droop and charge offset will vary linearly with capacitance
from the values given in the specification table for a 0.001µF
capacitor. With a capacitor of 0.01µF, the droop will reduce
to approximately 2.5µV/ms and the charge offset to approxi-
mately 1.5mV. The behavior of acquisition time with changes
in external capacitance is shown in the Typical Performance
Curves.
OFFSET ADJUSTMENT
The offset should be adjusted with the input grounded.
During the adjustment, the sample/hold should be switching
continuously between the Sample and the Hold mode. The
error should then be adjusted to zero when the unit is in the
Hold mode. In this way, charge offset as well as amplifier
offset will be adjusted. When a 0.001µF capacitor is used, it
will not be possible to adjust the full offset error at the
sample/hold. It should be adjusted elsewhere in the system.
APPLICATIONS
DATA ACQUISITION
The SHC298 may be used to hold data for conversion with
an analog-to-digital converter or used to provide Pulse
Amplitude Modulation (PAM) data output (see Figures 2
and 3).
DATA DISTRIBUTION
The SHC298 may be used to hold the output of a digital-to-
analog converter whose digital inputs are multiplexed (see
Figure 4).
With a 0.1µF storage capacitor, the output may be held 10
seconds with less than 0.1% error. With a 1µF storage
capacitor, the output may be held more than 15 minutes with
less than 1% error.
CAPACITIVE LOADING
SHC298 is sensitive to capacitive loading on the output and
may oscillate. When driving long lines, a buffer should be
used.
HIGH SPEED DATA ACQUISITION
The minimum sample time for one channel in a data acqui-
sition system is usually considered to be the acquisition time
of the sample/hold plus the conversion time of the analog-to-
digital converter. If two or more sample/holds are used with
a high-speed multiplexer, the acquisition time of the sample/
hold can be virtually eliminated. While the first channel is in
hold and switched on to the ADC, the multiplexer may be
addressed to the next channel. The second sample/hold will
have acquired this data by the time the conversion is com-
plete. Then, the sample/holds reverse roles and another
channel is addressed (see Figure 5). For low-level systems,
and instrumentation amplifier and double-ended multiplexer
may be connected to the sample/hold inputs. The settling
time of the multiplexer, instrumentation amplifier, and
sample/hold can be eliminated from the channel conversion
time as before.
Analog
Inputs
Analog
Multiplexer
–15VDC
0.1µF
0.005µF
Storage
To A/D
Converter
4
6
3
5
SHC298
8
7
2
1
PAM
Output
Mode
Control
0.1µF
1kΩ
24kΩ
+15VDC
FIGURE 2. Data Acquisition.
Actual Input
PAM Output
TEST SYSTEMS
The SHC298 is also well suited for use in test systems to
acquire and hold data transients for human operators or for
the other parts of the test system such as comparators, digital
voltmeters, etc.
Mode Control Hold
FIGURE 3. PAM Output.
®Teflon, DuPont de Nemours
®
7
SHC298/298A