ADS8481 Datasheet, PDF (7/31 Pages) Burr-Brown (TI) – 18-BIT, 1-MSPS, PSEUDO-DIFFERENTIAL UNIPOLAR INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE AND REFERENCE

ADS8481
www.ti.com
SLAS385A – FEBRUARY 2006 – REVISED MARCH 2006
TIMING CHARACTERISTICS
All specifications typical at –40°C to 85°C, +VA = 5 V +VBD = 3 V ^(1)(2)(3)
PARAMETER
t_(CONV)
t_(ACQ)
t_(HOLD)
t_pd1
t_pd2
t_pd3
t_w1
t_su1
t_w2
Conversion time
Acquisition time
Sample capacitor hold time
CONVST low to BUSY high
Propagation delay time, end of conversion to BUSY low
Propagation delay time, start of convert state to rising edge of BUSY
Pulse duration, CONVST low
Setup time, CS low to CONVST low
Pulse duration, CONVST high
CONVST falling edge jitter
t_w3
Pulse duration, BUSY signal low
t_w4
Pulse duration, BUSY signal high
t_h1
Hold time, first data bus transition (RD low, or CS low for read cycle, or BYTE or
BUS18/16 input changes) after CONVST low
t_d1
Delay time, CS low to RD low
t_su2
Setup time, RD high to CS high
t_w5
Pulse duration, RD low
t_en
Enable time, RD low (or CS low for read cycle) to data valid
t_d2
Delay time, data hold from RD high
t_d3
Delay time, BUS18/16 or BYTE rising edge or falling edge to data valid
t_w6
Pulse duration, RD high
t_w7
Pulse duration, CS high
t_h2
Hold time, last RD (or CS for read cycle ) rising edge to CONVST falling edge
t_pd4
Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling
edge
t_d4
Delay time, BYTE edge to BUS18/16 edge skew
t_su3
Setup time, BYTE or BUS18/16 transition to RD falling edge
t_h3
Hold time, BYTE or BUS18/16 transition to RD falling edge
t_dis
Disable time, RD high (CS high for read cycle) to 3-stated data bus
t_d5
Delay time, BUSY low to MSB data valid delay
t_d6
Delay time, CS rising edge to BUSY falling edge
t_d7
Delay time, BUSY falling edge to CS rising edge
t_su5
BYTE transition setup time, from BYTE transition to next BYTE transition, or BUS18/16
transition setup time, from BUS18/16 to next BUS18/16.
t_su(ABORT) Setup time from the falling edge of CONVST (used to start the valid conversion) to the
next falling edge of CONVST (when CS = 0 and CONVST are used to abort) or to the
next falling edge of CS (when CS is used to abort).
MIN TYP
250
40
20
20
t_(ACQ)min
40
0
0
50
5
10
20
20
50
0
0
10
10
50
50
50
70
MAX
710
25
40
25
25
10
710
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
30 ns
ns
30 ns
ns
ns
ns
ns
ns
ns
ns
30 ns
0 ns
ns
ns
ns
620 ns
(1) All input signals are specified with t_r = t_f = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (V_IL + V_IH)/2.
(2) See timing diagrams.
(3) All timing are measured with 20-pF equivalent loads on all data bits and BUSY pins.
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