ADS8380 Datasheet, PDF (7/29 Pages) Burr-Brown (TI) – 18-BIT, 600-kHz, PSEUDO-DIFFERENTIAL INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH SERIAL INTERFACE AND REFERENCE

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ADS8380
SLAS387A – NOVEMBER 2004 – REVISED DECEMBER 2004
PIN ASSIGNMENTS
TOP VIEW
1 _SB/2C
2 _AGND
3 +VA
4 _AGND
5 _AGND
6 +VA
7 _REFM
ADS8380
BDGND 21
+VBD ²⁰
AGND 19
AGND ¹⁸
+VA 17
+VA 16
AGND 15
TERMINAL FUNCTIONS
PIN
I/O
NAME
NO.
DESCRIPTION
AGND
2, 4, 5, 15, – Analog ground pins. AGND must be shorted to analog ground plane below the device.
18, 19
BDGND
21
– Digital ground for all digital inputs and outputs. BDGND must be shorted to the analog ground plane below
the device.
BUSY
22
O Status output. This pin is high when conversion is in progress.
CONVST
25
I Convert start. This signal is qualified with CS internally.
CS
26
I Chip select
FS
27
I Frame sync. This signal is qualified with CS internally.
+IN
11
I Noninverting analog input channel
–IN
12
I Inverting analog input channel
NC
10, 13
– No connection
PD
28
I Power down. Device resets and powers down when this signal is high.
REFIN
8
I Reference (positive) input. REFIN must be decoupled with REFM pin using 0.1-µF bypass capacitor and
1-µF storage capacitor.
REFM
7
I Reference ground. To be connected to analog ground plane.
REFOUT
9
O Internal reference output. Shorted to REFIN pin only when internal reference is used.
SB/2C
1
I Straight binary or 2's complement output data format. When low the device output is straight binary format;
when high the device output is 2's complement format. See Table 1.
SCLK
24
I Serial clock. Data is shifted onto SDO with the rising edge of this clock. This signal is qualified with CS
internally.
SDO
23
O Serial data out. All bits except MSB are shifted out at the rising edge of SCLK.
+VA
3, 6, 14, – Analog power supplies
16, 17
+VBD
20
– Digital power supply for all digital inputs and outputs.
7