ADS7815 Datasheet, PDF (6/8 Pages) Burr-Brown (TI) – 16-Bit 250kHz Sampling CMOS ANALOG-to-DIGITAL CONVERTER

TIMING
The timing shown in Figure 2 and Table II is the recom-
mended method of operating the ADS7815. The falling edge
of CS initiates the conversion. During the conversion, the
digital outputs are tri-stated and BUSY is LOW. Near the
end of the conversion, the digital outputs become active with
the most recent conversion result. After a brief delay (see
time t₁₁ in Figure 2 and Table II), BUSY rises. The rising
edge of BUSY is used to latch the digital result in Figure 1.
R/C AND CS
The R/C (read/convert) and CS signals control the start of
conversion and, when a conversion is not in progress, the
status of the digital outputs D15 through D0. It is possible to
start a conversion by taking CS LOW and then taking R/C
LOW. However, this is not recommended and will result in
a significant decrease in signal-to-noise ratio. This is due to
the digital outputs tri-stating while the sample and hold
transitions to the hold mode. The change in digital outputs
results in noise being coupled onto the hold capacitor.
If a conversion is not in progress or is just about to finish, the
digital outputs will be active when R/C is HIGH and CS is
LOW. This is shown in Figure 2 and Figure 3. It is possible
to return CS HIGH during the initial part of the conversion
(as is done with R/C) and prevent the digital outputs from
becoming active. At a later time, the digital results could be
read by taking CS LOW. It is also possible to leave R/C
LOW, take CS HIGH during the conversion, and read the
results at a later time by taking R/C HIGH and CS LOW.
Following a conversion, if R/C and CS are both LOW 250ns
after BUSY rises, then a new conversion will be initiated
without allowing the proper acquisition period for the sample
and hold. R/C must remain HIGH or CS must be taken
HIGH within 250ns of BUSY rising.
SYMBOL
DESCRIPTION
MIN
t₁
CS to R/C Delay
t₂
CS to BUSY Delay
t₃
Aperture Delay
t₄
BUSY LOW
t₅
R/C LOW to CS LOW
100
t₆
BUSY HIGH to CS HIGH
t₇
Bus Access Time
t₈
Bus Relinquish Time
t₉
Throughput Time
t₁₀
Conversion Time
t₁₁
Data Valid to BUSY HIGH 25
t₁₂
CS to R/C Setup Time
40
TABLE II. Conversion Timing.
TYP MAX UNITS
200
ns
40
ns
40
ns
3.3
µs
ns
250
ns
10
83
ns
83
ns
4
µs
3.3
µs
35
ns
ns
t₁₂
R/C
t₇
t₈
CS
D15 - D0 Hi-Z State
DataValid
Hi-Z State
MODE
Acquire
FIGURE 3. Bus Timing.
t₁
R/C
CS
t₂
BUSY
D15 - D0
MODE
t₃
Acquire
FIGURE 2. ADS7815 Timing.
®
ADS7815
t₅
t₉
t₄
Hi-Z State
Convert
t₁₀
t₆
DataValid
t₁₁
t₈
Hi-Z State
Acquire
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