CS8952T Datasheet, PDF (52/86 Pages) Cirrus Logic – 100BASE E-X AND 10BASE-T TRANSCEIVER

CS8952T
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
PCS Sub-Layer Configuration Register - Address 17h
15
Reserved
14
Time-Out
Select
13
Time-Out
Disable
12
Repeater
Mode
11
LED5 Mode
10
9
Unlock Regs
MR Preamble
Enable
8
Fast Test
7
6
5
CLK25 Dis-
able
Enable LT/100
CIM Disable
4
Tx Disable
3
Rx Disable
2
LED1 Mode
1
0
LED4 Mode Digital Reset
BIT
NAME
15 Reserved
14 Time-Out Select
13 Time-Out Disable
12 Repeater Mode
11 LED5 Mode
TYPE
RESET
DESCRIPTION
Read/Write 1
This bit is reserved and should be cleared to 0.
Read/Write 0
When this bit is set, the time-out counter in the
receive descrambler is set to time-out after 2 ms with-
out IDLES. When clear the counter is set to time-out
after 722 ms without IDLES.
Read/Write 0
When this bit is set, the time-out counter in the
receive descrambler is disabled. When this bit is
clear, the time-out counter is enabled.
Read/Write Reset to the value This bit defines the mode of the Carrier Sense (CRS)
on the REPEATER signal. When this bit is set, CRS is asserted due to
pin.
receive activity only. When this bit is clear, CRS is
asserted due to either transmit or receive activity.
Read/Write 0
This bit defines the mode of Pin LED5. When this bit
is set, pin LED5 indicates the synchronization status
of the 100BASE-TX descrambler. When this bit is
clear, LED5 indicates a collision.
10 Unlock Regs
Read/Write 0
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, this bit unlocks certain read only control
registers for factory testing. Leave clear for proper
operation.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
52
DS206TPP2