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DDC118 Datasheet, PDF (5/30 Pages) Burr-Brown (TI) – Octal Current Input 20-Bit Analog-To-Digital Converter
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DDC118
www.ti.com
PIN CONFIGURATION
Top View
SBAS325A − JUNE 2004 − REVISED JUNE 2005
QFN
48 47 46 45 44 43 42 41 40 39 38 37
DOUT 1
DOUT 2
CLK_4X 3
FORMAT 4
HISPD/LOPWR 5
RANGE0 6
RANGE1 7
RANGE2 8
AGND 9
VREF 10
AGND 11
AGND 12
DDC118
36 DIN
35 DIN
34 NC
33 NC
32 RESET
31 TEST
30 DGND
29 DGND
28 AGND
27 AVDD
26 AGND
25 AGND
13 14 15 16 17 18 19 20 21 22 23 24
PIN DESCRIPTIONS
PIN
NUMBER
DOUT
1
DOUT
2
CLK_4X
3
FORMAT
4
HISPD/LOPWR
5
RANGE0
6
RANGE1
7
RANGE2
8
AGND
9, 11-13, 18, 19, 24-26, 28
VREF
10
AIN8
14
AIN7
16
AIN6
20
AIN5
22
AIN4
15
AIN3
17
AIN2
21
AIN1
23
AVDD
27
DGND
29, 30, 38, 41, 43, 45, 47, 48
TEST
31
RESET
32
NC
33, 34
DIN
35
DIN
36
DVDD
37
DCLK
39
DCLK
40
CLK
42
DVALID
44
CONV
46
FUNCTION
Digital Output
Digital Output
Digital Input
Digital Input
Digital Input
Digital Input
Digital Input
Digital Input
Analog
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog
Digital
Digital Input
Digital Input
—
Digital Input
Digital Input
Digital
Digital Input
Digital Input
Digital Input
Digital Output
Digital Input
DESCRIPTION
Serial Data Output
Serial Data Output: Complementary Signal (optional, see text on page 13)
Master Clock Divider Control: 0 = divide by 1, 1 = divide by 4
Digital Output Word Format: 0 = 16 Bits, 1 = 20 Bits
Mode Control: 0 = Low-Power, 1 = High-Speed
Range Control 0 (least significant bit)
Range Control 1
Range Control 2 (most significant bit)
Analog Ground
External Voltage Reference Input, 4.096V Nominal
Analog Input 8
Analog Input 7
Analog Input 6
Analog Input 5
Analog Input 4
Analog Input 3
Analog Input 2
Analog Input 1
Analog Power Supply, 5V Nominal
Digital Ground
Test Mode Control
Resets the Digital Circuitry, Active Low
No connection. These pins must be left unconnected.
Serial Data Input: Complementary Signal (optional, see text on page 13)
Serial Data Input
Digital Power Supply, 3V Nominal
Serial Data Clock Input: Complementary Signal (optional, see text on page 13)
Serial Data Clock Input
Master Clock Input
Data Valid Output, Active Low
Conversion Control Input: 0 = Integrate on Side B, 1 = Integrate on Side A
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