DAC2900 Datasheet, PDF (5/17 Pages) Burr-Brown (TI) – Dual, 10-Bit, 125MSPS DIGITAL-TO-ANALOG CONVERTER

TIMING DIAGRAM
DATA IN
WRT1
WRT2
CLK1
CLK2
I_OUT1
I_OUT2
t_S
t_H
D[9:0]_(n)
t_LPW
t_CPW
D[9:0]_{(n + 1)}
t_CW
50%
t_SET
I_OUT(n)
t_PD
I_{OUT(n + 1)}
SYMBOL
t_S
t_H
t_LPW, t_CPW
t_CW
t_PD
t_SET
DESCRIPTION
MIN
TYP
MAX
UNITS
Input Setup Time
2
Input Hold Time
1.5
Latch/Clock Pulsewidth
3.5
Delay Rising CLK Edge to
0
Rising WRT Edge
Propagation Delay
Settling Time (0.1%)
ns
ns
4
ns
t_PW – 2
ns
1
ns
30
ns
DIGITAL INPUTS AND TIMING
The data input ports of the DAC2900 accepts a standard
positive coding with data bit D9 being the most significant
bit (MSB). The converter outputs support a clock rate of up
to 125MSPS. The best performance will typically be achieved
with a symmetric duty cycle for write and clock; however,
the duty cycle may vary as long as the timing specifications
are met. Also, the set-up and hold times may be chosen
within their specified limits.
All digital inputs of the DAC2900 are CMOS compatible.
The logic thresholds depend on the applied digital supply
voltages, such that they are set to approximately half the
supply voltage; V^th = +V_D/2 (±20% tolerance). The DAC2900
is designed to operate with a digital supply (+V_D) of +3.0V
to +5.5V.
The two converter channels within the DAC2900 consist of
two independent, 10-bit, parallel data ports. Each DAC-
channel is controlled by its own set of write (WRT1, WRT2)
and clock (CLK1, CLK2) inputs. Here, the WRT lines
control the channel input latches and the CLK lines control
the DAC latches. The data is first loaded into the input latch
by a rising edge of the WRT line. This data is presented to
the DAC latch on the following falling edge of the WRT
signal. On the next rising edge of the CLK line, the DAC is
updated with the new data and the analog output signal will
change accordingly. The double latch architecture of the
DAC2900 results in a defined sequence for the WRT and
CLK signals, expressed by parameter ‘t_CW’. A correct tim-
ing is observed when the rising edge of CLK occurs at the
same time, or before, the rising edge of the WRT signal. This
condition can simply be met by connecting the WRT and
CLK lines together. Note that all specifications were mea-
sured with the WRT and CLK lines connected together.
DAC2900
5
SBAS166B