MSC1202 Datasheet, PDF (45/78 Pages) Burr-Brown (TI) – Precision, Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) with 8051 Microcontroller and Flash Memory

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Configuration Address Register (CADDR) (write-only)
7
6
5
4
3
SFR 93h
MSC1201
MSC1202
SBAS317B − APRIL 2004 − REVISED JANUARY 2005
2
1
0
Reset Value
00h
CADDR
bits 7−0
Configuration Address Register. This register supplies the address for reading bytes in the 64 bytes of Flash
Configuration Memory. Always use the Boot ROM CADDR access routine (faddr_data_read). This register is also
used for SFR read and write routines.
CAUTION: If this register is written to while executing from Flash Memory, the CDATA register will be incorrect.
Configuration Data Register (CDATA) (read-only)
7
6
5
4
3
2
1
SFR 94h
0
Reset Value
00h
CDATA
bits 7−0
Configuration Data Register. This register will contain the data in the 64 bytes of Flash Configuration Memory that
is located at the last written address in the CADDR register. This is a read-only register.
Serial Port 0 Control (SCON0)
SFR 98h
7
SM0_0
6
SM1_0
5
SM2_0
4
REN_0
3
TB8_0
2
RB8_0
1
TI_0
0
RI_0
Reset Value
00h
SM0−2
bits 7−5
Serial Port 0 Mode. These bits control the mode of serial Port 0. Modes 1, 2, and 3 have 1 start and 1 stop bit in
addition to the 8 or 9 data bits.
MODE
0
0
1
1
2
SM0
0
0
0
0
1
SM1
0
0
1
1
0
SM2
0
1
0
1
0
FUNCTION
Synchronous
Synchronous
Asynchronous
Asynchronous−Valid Stop Required(2)
Asynchronous
2
1
0
1 Asynchronous with Multiprocessor Communication
3
1
1
0 Asynchronous
3
1
1
1 Asynchronous with Multiprocessor Communication(3)
(1) _{pCLK will be equal to tCLK, except that pCLK will stop for IDLE.}
(2) _{RI_0 will only be activated when a valid STOP is received.}
(3) _{RI_0 will not be activated if bit 9 = 0.}
LENGTH
8 bits
8 bits
10 bits
10 bits
11 bits
11 bits
11 bits
11 bits
PERIOD
12 pCLK(1)
4 pCLK(1)
Timer 1 Baud Rate Equation
Timer 1 Baud Rate Equation
64 pCLK(1) (SMOD = 0)
32 pCLK(1) (SMOD = 1)
64 pCLK(1) (SMOD = 0)
32 pCLK(1) (SMOD = 1)
Timer 1 Baud Rate Equation
Timer 1 Baud Rate Equation
REN_0
bit 4
Receive Enable. This bit enables/disables the serial Port 0 received shift register.
0: Serial Port 0 reception disabled.
1: Serial Port 0 received enabled (modes 1, 2, and 3). Initiate synchronous reception (mode 0).
TB8_0
bit 3
9th Transmission Bit State. This bit defines the state of the 9th transmission bit in serial Port 0 modes 2 and 3.
RB8_0
bit 2
9th Received Bit State. This bit identifies the state of the 9th reception bit of received data in serial Port 0 modes
2 and 3. In serial port mode 1, when SM2_0 = 0, RB8_0 is the state of the stop bit. RB8_0 is not used in mode 0.
TI_0
bit 1
Transmitter Interrupt Flag. This bit indicates that data in the serial Port 0 buffer has been completely shifted out. In serial
port mode 0, TI_0 is set at the end of the 8th data bit. In all other modes, this bit is set at the end of the last data bit.
This bit must be manually cleared by software.
RI_0
bit 0
Receiver Interrupt Flag. This bit indicates that a byte of data has been received in the serial Port 0 buffer. In serial
port mode 0, RI_0 is set at the end of the 8th bit. In serial port mode 1, RI_0 is set after the last sample of the incoming
stop bit subject to the state of SM2_0. In modes 2 and 3, RI_0 is set after the last sample of RB8_0. This bit must
be manually cleared by software.
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