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ADS820 Datasheet, PDF (4/14 Pages) Burr-Brown (TI) – 10-Bit, 20MHz Sampling ANALOG-TO-DIGITAL CONVERTER
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PIN CONFIGURATION
TOP VIEW
SOIC/SSOP
GND 1
Bit 1(MSB) 2
Bit 2 3
Bit 3 4
Bit 4 5
Bit 5 6
Bit 6 7
Bit 7 8
Bit 8 9
Bit 9 10
Bit 10 (LSB) 11
DNC 12
DNC 13
GND 14
ADS820
28 GND
27 IN
26 IN
25 GND
24 +VS
23 REFT
22 CM
21 REFB
20 +VS
19 MSBI
18 OE
17 +VS
16 CLK
15 +VS
DNC: Do Not Connect
PIN DESCRIPTIONS
PIN DESIGNATOR DESCRIPTION
1
GND
Ground
2
B1
Bit 1, Most Significant Bit
3
B2
Bit 2
4
B3
Bit 3
5
B4
Bit 4
6
B5
Bit 5
7
B6
Bit 6
8
B7
Bit 7
9
B8
Bit 8
10
B9
Bit 9
11
B10
Bit 10, Least Significant Bit
12
DNC
Do not connect.
13
DNC
Do not connect.
14
GND
Ground
15
+VS
+5V Power Supply
16
CLK
Convert Clock Input, 50% Duty Cycle
17
+VS
+5V Power Supply
18
OE
HI: High Impedance State. LO or Floating: Nor-
mal Operation. Internal pull-down resistor.
19
MSBI
Most Significant Bit Inversion, HI: MSB inverted
for complementary output. LO or Floating: Straight
output. Internal pull-down resistor.
20
+VS
+5V Power Supply
21
REFB
Bottom Reference Bypass. For external bypass-
ing of internal +1.25V reference.
22
CM
Common-Mode Voltage. It is derived by (REFT +
REFB)/2.
23
REFT
Top Reference Bypass. For external bypassing
of internal +3.25V reference.
24
+VS
+5V Power Supply
25
GND
Ground
26
IN
Input
27
IN
Complementary Input
28
GND
Ground
TIMING DIAGRAM
CONVERT
CLOCK
INTERNAL
TRACK/HOLD
OUTPUT
DATA
tCONV
tD
Track
Hold
"N"
tL
tH
DATA LATENCY
(1)
(6.5 Clock Cycles)
Hold
Hold
Hold
Hold
Hold
Hold
Track "N + 1" Track "N + 2" Track "N + 3" Track "N + 4" Track "N + 5" Track "N + 6" Track
Data Valid
N-8
Data Valid
N-7
Data Valid
N-6
N-5
Data Invalid
N-4
N-3
t2
N-2
N-1
N
t1
SYMBOL
DESCRIPTION
MIN
TYP
MAX UNITS
tCONV
tL
tH
tD
t1
t2
Convert Clock Period
50
Clock Pulse Low
24
Clock Pulse High
24
Aperture Delay
Data Hold Time, CL = 0pF
3.9
New Data Delay Time, CL = 15pF max
100µs
ns
25
ns
25
ns
2
ns
ns
12.5
ns
NOTE: (1) “ ” indicates the portion of the waveform that will stretch out at slower sample rates.
®
ADS820
4
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