ADS8329 Datasheet, PDF (33/42 Pages) Texas Instruments – LOW POWER, 16-BIT, 1-MHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE

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ADS8329
ADS8330
SLAS516 – DECEMBER 2006
Care must be given to handle the multiple CS signals when the converters are operating in chain mode. The
different chip select signals must be low for the entire data transfer (in this example 48 bits for three converters).
The first 16-bit word after the falling chip select is always the data from the chip that received the chip select
signal.
Case 1: If chip select is not toggled (CS stays low), the next 16 bits are data from the upstream converter, and
so on. This is shown in Figure 60. If there is no upstream converter in the chain, as converter #1 in the example,
the same data from the converter is going to be shown repeatedly.
Case 2: If the chip select is toggled during a chain mode data transfer cycle, as illustrated in Figure 61, the
same data from the converter is read out again and again in all three discrete 16-bit cycles. This is not a desired
result.
Cascaded Manual Trigger/Read While Sampling
(Use internal CCLK, EOC, and INT polarity programmed as active low)
CS held low during the N times 16 bits transfer cycle.
CONVST #1,
CONVST #2,
CONVST #3
These SCLKs are optional.
EOC #1
(active low)
INT #1
(active low)
Nth
t_CONV = 18 CCLKs
t_SAMPLE1 = 3 CCLKs min
t_d(EOS-CSF) = 20 ns min
t_d(CSR-EOS) = 20 ns min
CS/FS #1
SCLK #1,
SCLK #2,
SCLK #3
SDO #1,
CDI #2
CS/FS #2
SCLK #2,
SDO #2,
CDI #3
CS/FS #3
SDO #3
SDI #1,
SDI #2,
SDI #3
1
16
Nth from #1
1
16
Nth from #1
t_d(EOS-CSF) =
20 ns min
N − 1th from #2
Nth from #3
1110............
CONFIGURE
Nth from #1
t_d(EOS-CSF) =
20 ns min
N − 1th from #2
1101b
READ Result
1
16
Nth from #1
t_d(CSR-EOS) =
20 ns min
Nth from #1
t_d(CSR-EOS) =
20 ns min
Nth from #1
1101b
READ Result
Figure 61. Simplified Cascade Mode Timing with Shared CONVST and Discrete CS
Figure 62 shows a slightly different scenario where CONVST is not shared by the second converter. Converters
#1 and #3 have the same CONVST signal. In this case, converter #2 simply passes previous conversion data
downstream.
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