ADSP-2101BS-100 Datasheet, PDF (32/64 Pages) Analog Devices – TigerSHARC Embedded Processor

ADSP-21xx
TIMING PARAMETERS (ADSP-2101/2105/2111/2115/2161/2163)
BUS REQUEST/GRANT
Parameter
Frequency
13 MHz 13.824 MHz 16.67 MHz 20 MHz 25 MHz Dependency
Min Max Min Max Min Max Min Max Min Max Min
Max
Unit
Timing Requirement:
t_BH BR Hold after CLKOUT High¹ 24.2
23.1
20
t_BS BR Setup before CLKOUT Low¹ 39.2
38.1
35
Switching Characteristic:
t_SD CLKOUT High to DMS,
PMS, BMS, RD, WR Disable
39.2
38.1
35
t_SDB DMS, PMS, BMS, RD, WR
0
0
0
Disable to BG Low
t_SE BG High to DMS, PMS,
0
0
0
BMS, RD, WR Enable
t_SEC DMS, PMS, BMS, RD, WR
9.2
8.1
5
Enable to CLKOUT High
17.5
15
0.25t_CK + 5
ns
32.5
30
0.25t_CK + 20
ns
32.5
30
0.25t_CK + 20 ns
0
0
0
ns
0
0
0
ns
2.5
1.5²
0.25t_CK – 10²
ns
NOTES
1_{If BR meets the tBS and tBH setup/hold requirements, it will be recognized in the current processor cycle; otherwise it is recognized in the following cycle. BR requires}
a pulse width greater than 10 ns.
2_{For 25 MHz only the minimum frequency dependency formula for tSEC = (0.25tCK – 8.5).}
Section 10.2.4, “Bus Request/Grant,” on page 212 of the ADSP-2100 Family User’s Manual (1st Edition, 1993) states that “When BR is recognized, the processor
responds immediately by asserting BG during the same cycle.” This is incorrect for the current versions of all ADSP-21xx processors: BG is asserted in the cycle after
BR is recognized. No external synchronization circuit is needed when BR is generated as an asynchronous signal.
CLKOUT
BR
CLKOUT
PMS, DMS
BMS, RD
WR
BG
t_BH
t_BS
t_SD
t_SDB
t_SEC
t_SE
Figure 31. Bus Request/Grant
–32–
REV. B