OPA641 Datasheet, PDF (3/13 Pages) Burr-Brown (TI) – Wideband Voltage Feedback OPERATIONAL AMPLIFIER

SPECIFICATIONS (CONT)
ELECTRICAL
T_A = +25°C, V_S = ±5V, R_L = 100Ω, C_L = 2pF, R_FB = 402Ω, and all four power supply pins are used unless otherwise noted.
PARAMETER
CONDITIONS
OPA641H, P, U
MIN
TYP
MAX
POWER SUPPLY
Specified Operating Voltage
Operating Voltage Range
Quiescent Current
Over Specified Temperature
TEMPERATURE RANGE
Specification: H, P, PB, U, UB
HSQ
Thermal Resistance
P
U
H
T_MIN to T_MAX
T_MIN to T_MAX
±5
±4.5
±15
±19
Ambient
–40
Ambient
θ_JA, Junction to Ambient
120
170
120
±5.5
±22
±24
+85
NOTE: (1) Slew rate is rate of change from 10% to 90% of output voltage step.
OPA641HSQ, PB, UB
MIN
TYP
MAX
*
*
*
*
*
*
*
*
*
–55
+125
*
*
*
UNITS
V
V
mA
mA
°C
°C
°C/W
°C/W
°C/W
ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
Basic Model Number
Package Code
H = 8-pin Sidebraze DIP
P = 8-pin Plastic DIP
U = 8-pin Plastic SOIC
Performance Grade Code
S = –55°C to +125°C
B⁽¹⁾ or No Letter = –40°C to +85°C
Reliability Screening
Q = Q-Screened (HSQ Model Only)
OPA641 ( ) ( ) ( Q )
NOTE: (1) The “B” grade of the SOIC package will be designated with a “B”. Refer
to the mechanical section for the location.
Supply .......................................................................................... ±5.5VDC
Internal Power Dissipation⁽¹⁾ ....................... See Applications Information
Differential Input Voltage ............................................................ Total V_CC
Input Voltage Range .................................... See Applications Information
Storage Temperature Range: H, HSQ .......................... –65°C to +150°C
P, PB, U, UB ................. –40°C to +125°C
Lead Temperature (soldering, 10s) .............................................. +300°C
(soldering, SOIC 3s) ....................................... +260°C
Junction Temperature (T_J ) ............................................................ +175°C
NOTE: (1) Packages must be derated based on specified θ _JA. Maximum
T_J must be observed.
PACKAGE INFORMATION
PIN CONFIGURATION
Top View
NC 1
Inverting Input 2
Non-Inverting Input 3
–V_S1 4
DIP/SOIC
8 +V_S2(1)
7 +V_S1
6 Output
5 –V_S2(1)
MODEL
OPA641H, HSQ
OPA641P, PB
OPA641U, UB
PACKAGE
8-Pin Cerdip
8-Pin DIP
8-Pin SOIC
PACKAGE DRAWING
NUMBER⁽¹⁾
157
006
182
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
ELECTROSTATIC
DISCHARGE SENSITIVITY
NOTE: (1) Making use of all four power supply pins is highly recommended,
although not required. Using these four pins, instead of just pins 4 and 7, will
lower the effective pin impedance and substantially lower distortion.
Electrostatic discharge can cause damage ranging from per-
formance degradation to complete device failure. Burr-Brown
Corporation recommends that all integrated circuits be handled
and stored using appropriate ESD protection methods.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet published speci-
fications.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
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OPA641