CS8405A Datasheet, PDF (29/36 Pages) Cirrus Logic – 96 KHZ DIGITAL AUDIO INTERFACE TRANSMITTER

CEN
V
U
AUDIO
OMCK
H/S
TXN
TXP
ORIG
CS8405A
16 C Bit Enable (Input) - Determines how the channel status data bits are input. When CEN is low, hard-
ware mode A is selected, where the COPY/C, ORIG, EMPH and AUDIO pins are used to enter selected
channel status data. When CEN is high, hardware mode B is selected, where the COPY/C pin is used to
enter serial channel status data.
17 Validity Bit (Input) - In hardware modes A and B, the V pin input determines the state of the validity bit
in the outgoing AES3 transmitted data. This pin is sampled on both edges of the ILRCK.
18 User Data Bit (Input) - In hardware modes A and B, the U pin input determines the state of the user
data bit in the outgoing AES3 transmitted data. This pin is sampled on both edges of the ILRCK.
19 Audio Channel Status Bit (Input) - In hardware mode A (CEN = 0), the AUDIO pin determines the state
of the audio/non audio Channel Status bit in the outgoing AES3 data stream.
21 Master Clock (Input) - The frequency must be only 256x the sample rate.
24 Hardware/Software Control Mode Select (Input) -Determines the method of controlling the operation
of the CS8405A, and the method of accessing CS and U data. In software mode, device control and CS
and U data access is primarily through the control port, using a microcontroller. Hardware mode pro-
vides an alternate mode of operation, and access to CS and U data is provided by dedicated pins. This
pin should be permanently tied to VL+ or DGND.
25 Differential Line Drivers (Output) - Transmitting AES3 data. The drivers are pulled low while the
26 CS8405A is in the reset state.
28 ORIG Channel Status Bit Control (Input) - In hardware mode A (CEN = 0), the ORIG and COPY/C
pins determine the state of the Copyright, Pro, and L Channel Status bits in the outgoing AES3 data
stream, see Table 2.
DS469PP4
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