CS49400 Datasheet, PDF (29/100 Pages) Cirrus Logic – Multi-Standard Audio Decoder Family

EXTA[19:0]
Valid
NV_CS
T_wrc
T_ds
NV_WE
NV_OE
T_dv
EXTD[7:0]
T_dh
LSP
Figure 21. SRAM/Flash Controller Timing Diagram - Single Byte Write Cycle
EXTA[19:0]
Valid
NV_CS
T_rdc
T_ds
NV_OE
NV_WE
T_su
EXTD[7:0]
T_dh
LSP
Figure 22. SRAM/Flash Controller Timing Diagram - Single Byte Read Cycle
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