CS4922 Datasheet, PDF (29/34 Pages) Cirrus Logic – MPEG/G.729A AUDIO DECODER SYSTEM

CS4922
EXTCK - External Clock Select, PIN 29.
Setting EXTCK high allows ALTCLK to be used as an input for an external VCO. Setting
EXTCK low disables ALTCLK. Note that EXTCK should be tied directly to either digital
power or ground for proper operation.
FLT - PLL Filter, PIN 31.
A capacitor (typically 0.47 µF) connected to this pin filters the control voltage for the on-chip
VCO. Trace length should be minimized to the pin.
CLKIN - Clock Input, PIN 27.
The 27 MHz clock input to the CLKIN is used to synchronize the PLL’s. It is typical for
SCLK for the audio data and CLKIN to be derived from the same clock source to avoid
asynchronous noise between the audio source and the DSP.
90_CLK - Optional SCR/PCR 33-Bit Counter Clock, PIN 19
The 90_CLK pin is an input clock signal (typically 90 kHz) which is used to clock the internal
33-bit counter. The 33-bit counter’s clock source is set to 90_CLK when DIV = 0 in the CM0
register. Otherwise when DIV = 1, the 33-bit counter will be clocked by CLKIN ÷ 300.
Control
DBCLK, DBDA - Debug Port, PINS 12, 13.
It is required that a pull-up be used (typically 2.2 kΩ) on pin 13.
RESET - PIN 41.
The CS4922 enters a reset state while RESET is low. When in reset condition, all internal
registers are set to 0, the digital audio transmitter, serial control port, and ALTCLK pin are
disabled, and the stereo DAC is muted. Normal operation is resumed one internal clock cycle
after the rising edge of RESET.
BOOT - PIN 40.
Boot enable pin. Pin must be set high to initiate the download of a program. While BOOT is
high, RESET must be toggled high. This starts the internal boot program.
XF1, XF2, XF3, XF4 - External Flags, PINS 20, 16, 15, 14.
The XF pins are software controllable outputs via the LINT register. These pins are open drain
so an external pullup is required (typically 2.2 kΩ) for proper operation of the pins.
PIO - PIN 30.
This pin should be grounded through a 10 kΩ resistor in normal operation.
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