CS62180 Datasheet, PDF(27/50 Page) Cirrus Logic

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CS62180 Datasheet, PDF (27/50 Pages) Cirrus Logic – T1 FRAMER

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CS62180B

rising edge before declaring synchronization.

SYNCC (RCR.3) allows you to modify the algo-

rithm employed to search for and qualify the

framing alignment. There are two different quali-

fying conditions available for each framing

mode, and the meaning of RCR.3 depends on

which framing mode has been selected via

CCR.4.

193S Resync

When operating with the 193S framing format,

RCR.3 selects whether or not the CS62180B

will qualify the FS bits during resync.

If a non-standard S-bit pattern is being used,

clearing RCR.3 will enable the device to first

search for the FT framing pattern to find frame

alignment, and then only reset multiframe align-

ment if the FS pattern can be found. This means

that if a valid FS pattern is not found, synchroni-

zation will be declared anyway, and the

multiframe alignment indicated by RMSYNC

may be false. The S-bits output on RLINK can

be used to decode framing externally in such ap-

plications.

When using standard FS signaling, setting

RCR.3 to a "1" will cause the device to cross

check the FT and FS patterns to find sync, and

both patterns must be valid before sync is de-

clared. Synchronization will be declared after the

number of FT bits selected by RCR.2 separated

by valid FS bits have been qualified. Note that

in either setting, S-bit format yellow alarms are

recognized by the synchronizer if they have been

selected by setting CCR.3.

193E Resync

Clearing RCR.3 while in 193E mode will cause

the CS62180B to use only the

FPS framing pattern when looking for a valid

framing alignment. If RCR.3 is set, the device

will attempt to qualify the CRC bits after a can-

DS225PP2

didate alignment has been found. If the CRC

codes match, then the new alignment will be de-

clared, if not, the device will try two more times.

If the third CRC code does not qualify, then the

device will start a new resync procedure and

continue in this manner until a framing align-

ment can be verified with the CRC codes.

Note that after 24 ms, if there are still multiple

candidates for framing alignment, the device will

test the CRC codes to eliminate false candidates

regardless of the setting of RCR.3. After the

framing alignment has been found, it takes about

9 ms for the device to check the CRC codes for

the first superframe. If that superframe fails, it

takes about 3 ms to check each additional CRC

code.

SLC-96Â® Resync

When operating with the SLC-96Â® framing for-

mat, the receiver should be programmed for

FS/FT cross-coupling (RCR.3=1) and for mini-

mum resync time (RCR.2=0). This causes the

CS62180B to sync on the 10 valid FT bits

seprated by valid Fs bits in frames 65 through

11, and prevents false synchronization to data

link and/or spoiler bits.

Note: The CS62180B does not check SLC-96Â®

multiframe alignment once synchronization is

declared. In applications such as test equipment

where the input data framing format may change

or the multiframe alignment may change when

the frame alignment does not, the datalink proc-

essor should check the phase between RSIGSEL

and the DL spoiler bits on RLINK and issue a

forced resync when multiframe alignment is in-

correct. In the SLC-96Â® applications, a forced

resync should be issued after the device is con-

figured. Since the CS62180B defaults to the

193S framing mode at power up it may sync to

SLC-96Â® data while in the 193S mode. If this

occurs the multiframe alignment may be incor-

rect after the CS62180B is programmed for

SLC-96Â® mode even though the frame alignment

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