ADS8413 Datasheet, PDF (27/38 Pages) Burr-Brown (TI) – 16-BIT, 2-MSPS, LVDS SERIAL INTERFACE, SAR ANALOG-TO-DIGITAL CONVERTER

ADS8413
www.ti.com
LAYOUT
SLAS490 – OCTOBER 2005
For optimum performance, care should be taken with the physical layout of the ADS8413 circuitry. The device
offers single-supply operation, and it is often used in close proximity with digital logic, FPGA, microcontrollers,
microprocessors, and digital signal processors. The more digital logic present in the design and the higher the
switching speed, the more difficult it is to achieve good performance from the converter.
The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground
connections, and digital inputs that occur just prior to the end of sampling and just prior to latching the output of
the analog comparator during the conversion phase. Such glitches might originate from switching power supplies,
nearby digital logic, or high power devices. Noise during the end of sampling and the later half of a conversion
must be kept to a minimum (the former half of a conversion is not very sensitive since the device uses a
proprietary error correction algorithm to correct for transient errors during this period).
The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the
external event. On average, the device draws very little current from an external reference as the reference
voltage is internally buffered. If the reference voltage is external and originates from an op amp, make sure that it
can drive the bypass capacitor or capacitors without oscillation. A 0.1-µF bypass capacitor and 1-µF storage
capacitor are recommended from REFIN directly to REFM.
The AGND and BDGND pins should be connected to a clean ground point. In all cases, this should be the
analog ground. Avoid connections that are too close to the grounding point of a microcontroller or digital signal
processor. If required, run a ground trace directly from the converter to the power supply entry point. The ideal
layout consists of an analog ground plane dedicated to the converter and associated analog circuitry.
As with the AGND connections, +VA should be connected to a +5-V power supply plane that is separate from the
connection for +VBD and digital logic until they are connected at the power entry point onto the PCB. Power to
the ADC should be clean and well bypassed. A 0.1-µF ceramic bypass capacitor should be placed as close to
the device as possible. See Table 5 for the placement of the capacitor. In addition to the 0.1-µF capacitor, a 1-µF
capacitor is recommended. In some situations, additional bypassing may be required, such as a 100-µF
electrolytic capacitor or even a Pi filter made up of inductors and capacitors; all designed to essentially low-pass
filter the +5-V supply, thus removing the high frequency noise.
Table 5. Power Supply Decoupling Capacitor Placement
POWER SUPPLY PLANE
SUPPLY PINS
CONVERTER ANALOG SIDE
Pair of pins require a shortest path to decoupling (9,10) (16,17) (20,21) (22,23) (26,27 or 25,26)
capacitors
(36,37)
CONVERTER DIGITAL SIDE
(44,45)
TYPICAL CHARACTERISTICS
HISTOGRAM (DC CODE SPREAD
AT THE CENTER OF CODE)
120000
100000
80000
+VA = 5 V,
T_A = 25°C,
f_s = 2 MSPS,
V_ref = 4.096 V
108126
60000
40000
20000
8
0
32763
8436
32764
32765
Code
20721
32766
7
32767
Figure 24.
HISTOGRAM (DC CODE SPREAD
WITH I/P CLOSE TO FS)
140000
120000
100000
+VA = 5 V,
T_A = 25°C,
f_s = 2 MSPS,
V_ref = 4.096 V
121865
80000
60000
40000
20000
0
8
65504
11013
65505
65506
Code
30724
65507
230
65508
Figure 25.
EFFECTIVE NUMBER OF BITS
vs
FREE-AIR TEMPERATURE
15.25
15.2
15.15
+VA = 5 V,
f_i = 1 kHz,
f_s = 2 MSPS,
V_ref = 4.096 V
15.1
15.05
15
14.95
14.9
14.85
14.8
14.75
−40 −20
0
20
40
60
80
T_A − Free-Air Temperature − °C
Figure 26.
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