CS44600 Datasheet, PDF (26/78 Pages) Cirrus Logic – 6-Channel Digital Amplifier Controller

4.4 FsIn Clock Domain Modules
CS44600
4.4.1 Digital Audio Input Port
The CS44600 interfaces to an external Digital Audio Processor via the Digital Audio Input serial port, the
DAI serial port. The DAI port has 3 stereo data inputs with support for I²S, left-justified and right-justified
formats. The DAI port operates in slave operation only, where DAI_LRCK, DAI_SCLK and DAI_MCLK are
always inputs. The signal DAI_LRCK must be equal to the sample rate, Fs and must be synchronously
derived from the supplied master clock, DAI_MCLK. The serial bit clock, DAI_SCLK, is used to sample
the data bits and must be synchronously derived from the master clock.
DAI_SDIN1, DAI_SDIN2, and DAI_SDIN3 are the serial data input pins supplying the associated internal
PWM channel modulators. The serial data interface format selection (left-justified, right-justified, I²S, one
line mode, or TDM) for the DAI serial port data input pins is configured using the appropriate bits in the
register “Misc. Configuration (address 04h)” on page 52. The serial audio data is presented in 2's comple-
ment binary form with the MSB first in all formats.
When operated in One Line Data Mode, 6 channels of PWM data are input on DAI_SDIN1. In TDM mode,
all 6 channels are multiplexed onto the DAI_SDIN1 data line. Table 2 outlines the serial port channel al-
locations.
Serial Data Inputs
Data mode
DAI_SDIN1
Normal (I²S,LJ,RJ)
One Line #1 or #2
TDM
DAI_SDIN2
Normal (I²S,LJ,RJ)
One Line #1 or #2
TDM
DAI_SDIN3
Normal (I²S,LJ,RJ)
One Line #1 or #2
TDM
Channel Assignments
PWMOUTA1(left channel)/PWMOUTB1(right channel)
PWMOUTA1/A2/A3/B1/B2/B3
PWMOUTA1/A2/A3/B1/B2/B3
PWMOUTA2(left channel)/PWMOUTB2(right channel)
not used
not used
PWMOUTA3(left channel)/PWMOUTB3(right channel)
not used
not used
Table 2. DAI Serial Audio Port Channel Allocations
The DAI digital audio serial ports support 6 formats with varying bit depths from 16 to 24 as shown in Fig-
ure 17, Figure 18, Figure 19, Figure 20, Figure 21 and Figure 22. These formats are selected using the
configuration bits in the “Misc. Configuration (address 04h)” on page 52.
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DS633PP1