OPA3832_07 Datasheet, PDF (25/32 Pages) Burr-Brown (TI) – Triple, Low-Power, High-Speed, Fixed-Gain Operational Amplifier

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A fine-scale output offset null, or dc operating point
adjustment, is often required. Numerous techniques
are available for introducing dc offset control into an
op amp circuit. Most of these techniques are based
on adding a dc current through the feedback resistor.
In selecting an offset trim method, one key
consideration is the impact on the desired signal
path frequency response. If the signal path is
intended to be noninverting, the offset control is best
applied as an inverting summing signal to avoid
interaction with the signal source. If the signal path is
intended to be inverting, applying the offset control to
the noninverting input may be considered. Bring the
dc offsetting current into the inverting input node
through resistor values that are much larger than the
signal path resistors. This configuration ensures that
the adjustment circuit has minimal effect on the loop
gain and thus the frequency response.
THERMAL ANALYSIS
Maximum desired junction temperature sets the
maximum allowed internal power dissipation, as
described below. In no case should the maximum
junction temperature be allowed to exceed +150°C.
Operating junction temperature (T_J) is given by
T_A + P_D × θ_JA. The total internal power dissipation
(P_D) is the sum of quiescent power (P_DQ) and
additional power dissipated in the output stage (P_DL)
to deliver load power. Quiescent power is simply the
specified no-load supply current times the total
supply voltage across the part. P_DL depends on the
required output signal and load, though for resistive
loads connected to midsupply (V_S/2), P_DL is at a
maximum when the output is fixed at a voltage equal
to V_S/4 or 3V_S/4. Under this condition, P_DL = V_S2/(4 ×
R_L), where R_L includes feedback network loading.
Note that it is the power in the output stage, and not
into the load, that determines internal power
dissipation.
As a worst-case example, compute the maximum T_J
using an OPA3832 (TSSOP-14 package) in the
circuit of Figure 48 operating at the maximum
specified ambient temperature of +85°C and driving
both channels at a 150Ω load at mid-supply.
P_D
10V
12.75mA
4
3 5²
150W 800W
276mV
Maximum T_J
85°C 0.276W 100°C W 113°C
Although this value is still well below the specified
maximum junction temperature, system reliability
considerations may require lower ensured junction
temperatures. The highest possible internal
OPA3832
SBOS370 – DECEMBER 2006
dissipation will occur if the load requires current to be
forced into the output at high output voltages or
sourced from the output at low output voltages. This
condition puts a high current through a large internal
voltage drop in the output transistors.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a
high-frequency amplifier such as the OPA3832
requires careful attention to board layout parasitics
and external component types. Recommendations
that will optimize performance include:
a) Minimize parasitic capacitance to any ac ground
for all of the signal I/O pins. Parasitic capacitance on
the output and inverting input pins can cause
instability; on the noninverting input, it can react with
the source impedance to cause unintentional
bandlimiting. To reduce unwanted capacitance, a
window around the signal I/O pins should be opened
in all of the ground and power planes around those
pins. Otherwise, ground and power planes should be
unbroken elsewhere on the board.
b) Minimize the distance ( < 0.25") from the
power-supply pins to high-frequency 0.1µF
decoupling capacitors. At the device pins, the ground
and power-plane layout should not be in close
proximity to the signal I/O pins. Avoid narrow power
and ground traces to minimize inductance between
the pins and the decoupling capacitors. Each
power-supply connection should always be
decoupled with one of these capacitors. An optional
supply decoupling capacitor (0.1µF) across the two
power supplies (for bipolar operation) will improve
2nd-harmonic distortion performance. Larger (2.2µF
to 6.8µF) decoupling capacitors, effective at lower
frequency, should also be used on the main supply
pins. These may be placed somewhat farther from
the device and may be shared among several
devices in the same area of the PCB.
c) Careful selection and placement of external
components will preserve the high-frequency
performance. Resistors should be a very low
reactance type. Surface-mount resistors work best
and allow a tighter overall layout. Metal film or
carbon composition axially-leaded resistors can also
provide good high-frequency performance. Again,
keep the leads and PCB traces as short as possible.
Never use wire-wound type resistors in a
high-frequency application. Since the output pin and
inverting input pin are the most sensitive to parasitic
capacitance, always position the series output
resistor, if any, as close as possible to the output pin.
Other network components, such as noninverting
input termination resistors, should also be placed
close to the package.
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