CS5368 Datasheet, PDF (22/39 Pages) Cirrus Logic – 114 dB, 192 kHz, 8-Channel A/D Converter

CS5368
4.3 Stand-Alone Operation
In Stand-Alone Mode, the CS5368 is programmed exclusively with multi-use configuration pins. This mode
provides a set of commonly used features. To utilize the complete set of device features, Control-Port Mode
needs to be used.
To use the CS5368 in Stand-Alone Mode, the configuration pins must be held in a stable state and RST
must be asserted until the power supplies and clocks are stable. Upon de-assertion of RST the state of the
configuration pins are latched, Vq stabilizes and the device starts sending audio output data.
4.4 Control-Port Operation
In Control-Port Mode, all features of the CS5368 are available. Four multi-use configuration pins become
software pins that support the I²C or SPI bus protocol. To initiate Control-Port Mode, a controller that sup-
ports I²C or SPI must be used to enable the internal register functionality. This is done by setting the
CP-EN bit (bit 7 of the Global Control Port Register). Once CP-EN is set, all of the device configuration pins
are ignored, and the internal register settings determine the operating modes of the part.
4.5 DC Offset Control
The CS5368 includes a dedicated high-pass filter for each channel to remove input DC offset at the system
level. If a DC level is present, clicks might be heard when switching between devices in a multichannel sys-
tem.
In Standalone Mode, all of the high pass filters remain enabled. In Control-Port Mode, the high pass filters
default to enabled, but may be controlled by writing to the HPF register. If any HPF bit is taken low, the re-
spective high-pass filter is enabled, and it continuously subtracts a measure of the DC offset from the output
of the decimation filter. If any HPF bit is taken high during device operation, the value of the DC offset reg-
ister is frozen, and this DC offset will continue to be subtracted from the conversion result.
4.6 Serial Audio Interface (SAI)
4.6.1 General Description
The SAI port consists of two timing pins, SCLK, LRCK/FS, and four audio data output pins,
SDOUT1/TDM, SDOUT2/TDM, SDOUT3/TDMC and SDOUT4/TDMC. The SAI port may be operated as
a timing master or a timing slave. The port supplies digital audio data in three standard formats, LJ, I²S
and TDM. Three sampling ranges are used to provide analog to digital audio conversion from 2 kHz to
216 kHz sampling rates.
The main TDM output port resides on the SDOUT1 pin. The remaining three TDM outputs are used to
balance device substrate noise. It is recommended that all four of these nets be routed and loaded iden-
tically for best device noise performance.
4.6.2 Master and Slave Operation
In Master mode, the CS5368 outputs SCLK and LRCK/FS which are synchronously derived from MCLK.
SCLK is the audio clock which shifts out the individual bits of each sample. In LJ and I²S format, LRCK/FS
signifies which channel of data is being shifted out. In TDM Mode, LRCK/FS acts as a frame synchroni-
zation signal. A high transition indicates the beginning of a new frame of 8 channels of serial data.
In Slave Mode, SCLK and LRCK/FS become inputs, and the signals must be supplied by another device.
The device may be another CS5368 or a microcontroller. Serial data is shifted out by the CS5368 in both
cases.
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