DDC101 Datasheet, PDF (21/27 Pages) Burr-Brown (TI) – 20-BIT ANALOG-TO-DIGITAL CONVERTER

0
–5
–10
–15
–20
–25
–30
–35
–40
100
N = 2000
M = 32
K = 16
1k
10k
Frequency (Hz)
100k
FIGURE 20. Product of Frequency Response of Basic Inte-
gration and Oversampling; 1ms Integration
Time, 32 Oversamples.
Figure 21 shows the frequency response of the DDC101 and
an ideal integrator with the same integration time. In this
comparison, the DDC101 has greater bandwidth to the first
null, but it also has greater out of band attenuation which
reduces broadband noise significantly. If desired, the fre-
quency response of the ideal integrator can be produced by
passing the DDC101 output through an external digital
filtering function which has the frequency response from DC
to Nyquist of
sin(πf T_INT ) _• πf T_{MEAS •} M sin(πf / f _CLK ) _.
πf T_INT sin(πf T_MEAS ) sin(πf M / f _CLK )
This has the effect of further attenuating undesired signals
(noise) outside the “passband”, further increasing the signal-
to-noise ratio of the DDC101 and closely emulating the ideal
integrator’s signal accumulation characteristics.
Comparison of DDC101 with Ideal Integrator
0
DDC101 with N = 2000;
–5
–10 Nyquist
–15 ^(fCONV/2)
L = 1; M = 256; K = 16;
T_CONV = T_INT = 2MHz/N = 1ms
f_MEAS = 2MHz/(N-M-K) = 1.16kHz
–20
Ideal Integrator
with T_INT = 1ms
–25
–30
–35
f_CONV
–40
100
1k f_MEAS
10k
Frequency (Hz)
100k
FIGURE 21. Comparison of DDC101 with Ideal Integrator.
SYSTEM SETUP
After power up, the Reset System and FDS signal inputs
should be held low (active), while the SETUP register is
loaded by the user. After the SETUP register is loaded, the
Reset System input should transition to inactive while the
FDS input remains active. The FDS should transition to
inactive at the start of operation. Thereafter, Reset System
should stay inactive and the FDS should be used to control
each integration cycle.
SETUP INPUT
Software Control
Many of the options of the DDC101 are set through a serial
bit stream transmitted by the user into the SETUP Input pin.
The 12-bit word transmitted into the SETUP Input is used to
set the following four options, in sequence:
1. Acquisition Time Control, K
2 bits
2. Oversampling Control
Samples/Integration, M
4 bits
3. Multiple Integration Control
Integrations/Conversion, L
4 bits
4. Unipolar or Bipolar Input Range 1 bit
5. Output Format
1 bit
Total for SETUP
12 bits
See Figure 5: SETUP Timing Diagram.
Acquisition Time Control, K
This signal sets the acquisition time (K clock periods) and
controls the use of Correlated Double Sampling. The acqui-
sition time occurs at the start of each new integration. The
acquisition time control can be set to four options: “no
CDS”, 1, 16 or 32 clock periods. For typical continuous
integration applications, K = 16 is recommended. The acqui-
sition time always begins with one clock period for reset.
This reset clock period is followed by 0, 15 or 31 clock
periods for signal acquisition. Correlated Double Sampling
is activated if the initial acquisition time is set to 1, 16 or 32
clock periods. Correlated Double Sampling is disabled and
the Initial Data Point is not acquired if “no CDS” is selected.
K
“No CDS”
1
16
32
RESET
CLOCKS
1
1
1
1
ACQUISITION
CLOCKS
0
0
15
31
TABLE IX. Acquisition Time Control, K.
CDS
Disabled
Enabled
Enabled
Enabled
When Correlated Double Sampling is activated, the DDC101
acquires the initial data point for error correction as part of
each conversion. At the end of the conversion cycle, the
initial data point is subtracted from the final data point. The
errors that are corrected with CDS are charge injection,
kT/C noise, and DDC101 voltage offset. When Correlated
Double Sampling is deactivated, the initial data point is not
taken.
®
21
DDC101