ADS5231 Datasheet, PDF (21/26 Pages) Burr-Brown (TI) – Dual, 12-Bit, 40MSPS, +3.3V Analog-to-Digital Converter

ADS5231
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DATA OUTPUT FORMAT (MSBI)
The ADS5231 makes two data output formats
available: the Straight Offset Binary code (SOB) or
the Binary Two's Complement code (BTC). The
selection of the output coding is controlled by the
MSBI (pin 41). Because the MSBI pin has an internal
pull-down, the ADS5231 will operate with the SOB
code as its default setting. Forcing the MSBI pin high
will enable BTC coding. The two code structures are
identical, with the exception that the MSB is inverted
for BTC format; as shown in Table 1.
OUTPUT ENABLE (OE)
Digital outputs of the ADS5231 can be set to
high-impedance (tri-state), exercising the output
enable pins, OE_A (pin 42), and OE_B (pin 6). Internal
pull-downs configure the output in enable mode for
normal operation. Applying a logic high voltage will
disable the outputs. Note that the OE-function is not
designed to be operated dynamically (that is, as a
fast multiplexer) because it may lead to corrupt
conversion results. Refer to the Electrical
Characteristics table to observe the specified tri-state
enable and disable times.
OVER-RANGE INDICATOR (OVR)
If the analog input voltage exceeds the full-scale
range set by the reference voltages, an over-range
condition exists. The ADS5231 incorporates a
function that monitors the input voltage and detects
any such out-of-range condition. This operation
functions for each of the two channels independently.
The current state can be read at the over-range
indicator pins (pins 9 and 39). This output is low
when the input voltage is within the defined input
SBAS295A – JULY 2004 – REVISED JANUARY 2007
range. It will change to high if the applied signal
exceeds the full-scale range. It should be noted that
each of the OVR outputs is updated along with the
data output corresponding to the particular sampled
analog input voltage. Therefore, the OVR state is
subject to the same pipeline delay as the digital data
(six clock cycles).
OUTPUT LOADING
It is recommended that the capacitive loading on the
data output lines be kept as low as possible,
preferably below 15pF. Higher capacitive loading will
cause larger dynamic currents as the digital outputs
are changing. Such high current surges can feed
back to the analog portion of the ADS5231 and
adversely affect device performance. If necessary,
external buffers or latches close to the converter
output pins may be used to minimize the capacitive
loading.
SERIAL INTERFACE
The ADS5231 has a serial interface that can be used
to program internal registers. The serial interface is
disabled if SEL is connected to 0.
When the serial interface is to be enabled, SEL
serves the function of a RESET signal. After the
supplies have stabilized, it is necessary to give the
device a low-going pulse on SEL. This results in all
internal registers resetting to their default value of 0
(inactive). Without a reset, it is possible that registers
may be in their non-default state on power-up. This
condition may cause the device to malfunction.
Table 1. Coding Table for Differential Input Configuration and 2V_PP Full-Scale Input Range
STRAIGHT OFFSET BINARY (SOB; MSBI = 0) BINARY TWO'S COMPLEMENT (BTC; MSBI = 1)
DIFFERENTIAL INPUT
D11............D0
D11............D0
+FS (IN = +2V, IN = +1V)
1111 1111 1111
0111 1111 1111
+1/2 FS
1100 0000 0000
0100 0000 0000
Bipolar Zero (IN = IN = CMV)
1000 0000 0000
0000 0000 0000
–1/2 FS
0100 0000 0000
1100 0000 0000
–FS (IN = +1V, IN = +2V)
0000 0000 0000
1000 0000 0000
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