OPA3681 Datasheet, PDF (20/21 Pages) Burr-Brown (TI) – Triple Wideband, Current-Feedback OPERATIONAL AMPLIFIER With Disable

40
Output Voltage
20
(0V Input)
0
–20
–40
V_DIS
4.8V
0.2V
Time (20ns/div)
FIGURE 14. Disable/Enable Glitch.
The transition edge rate (dv/dt) of the DIS control line will
influence this glitch. For the plot of Figure 14, the edge rate
was reduced until no further reduction in glitch amplitude
was observed. This approximately 1V/ns maximum slew
rate may be achieved by adding a simple RC filter into the
V_DIS pin from a higher speed logic line. If extremely fast
transition logic is used, a 2kΩ series resistor between the
logic gate and the V_DIS input pin will provide adequate
bandlimiting using just the parasitic input capacitance on the
V_DIS pin while still ensuring adequate logic level swing.
THERMAL ANALYSIS
Due to the high output power capability of the OPA3681,
heatsinking or forced airflow may be required under extreme
operating conditions. Maximum desired junction tempera-
ture will set the maximum allowed internal power dissipa-
tion as described below. In no case should the maximum
junction temperature be allowed to exceed 175°C. Operating
junction temperature (T_J) is given by T_A + P_D • θ_JA. The total
internal power dissipation (P_D) is the sum of quiescent
power (P_DQ) and additional power dissipation in the output
stage (P_DL) to deliver load power. Quiescent power is simply
the specified no-load supply current times the total supply
voltage across the part. P_DL will depend on the required
output signal and load but would, for a grounded resistive
load, be at a maximum when the output is fixed at a voltage
equal to 1/2 of either supply voltage (for equal bipolar
supplies). Under this condition, P_DL = V_S2/(4 • R_L) where R_L
includes feedback network loading.
Note that it is the power in the output stage and not into the
load that determines internal power dissipation.
As a worst-case example, compute the maximum T_J using an
OPA3681 SO-16 (in the circuit of Figure 1), operating at the
maximum specified ambient temperature of +85°C with all
three outputs driving a grounded 20Ω load to +2.5V:
P_D = 10V • 19.2mA + 3 • [5²/(4 • (20Ω || 998Ω))] = 1.15W
Maximum T_J = +85°C + (1.15 • 100°C/W) = 200°C
This absolute worst-case condition exceeds specified maxi-
mum junction temperature. Normally this extreme case will
not be encountered. Careful attention to internal power
dissipation is required and perhaps airflow considered under
extreme conditions.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high frequency
amplifier like the OPA3681 requires careful attention to
board layout parasitics and external component types. Rec-
ommendations that will optimize performance include:
a) Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the output
and inverting input pins can cause instability: on the non-
inverting input, it can react with the source impedance to
cause unintentional bandlimiting. To reduce unwanted ca-
pacitance, a window around the signal I/O pins should be
opened in all of the ground and power planes around those
pins. Otherwise, ground and power planes should be unbro-
ken elsewhere on the board.
b) Minimize the distance (< 0.25") from the power supply
pins to high frequency 0.1µF decoupling capacitors. At the
device pins, the ground and power plane layout should not
be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between
the pins and the decoupling capacitors. The power supply
connections (on pins 4 and 7) should always be decoupled
with these capacitors. An optional supply de-coupling ca-
pacitor across the two power supplies (for bipolar operation)
will improve 2nd harmonic distortion performance. Larger
(2.2µF to 6.8µF) decoupling capacitors, effective at lower
frequency, should also be used on the main supply pins.
These may be placed somewhat farther from the device and
may be shared among several devices in the same area of the
PC board.
c) Careful selection and placement of external compo-
nents will preserve the high frequency performance of
the OPA3681. Resistors should be a very low reactance
type. Surface-mount resistors work best and allow a tighter
overall layout. Metal-film and carbon composition, axially
leaded resistors can also provide good high frequency per-
formance. Again, keep their leads and PC board trace length
as short as possible. Never use wirewound type resistors in
a high frequency application. Since the output pin and
inverting input pin are the most sensitive to parasitic capaci-
tance, always position the feedback and series output resis-
tor, if any, as close as possible to the output pin. Other
network components, such as non-inverting input termina-
tion resistors, should also be placed close to the package.
Where double-side component mounting is allowed, place
the feedback resistor directly under the package on the other
side of the board between the output and inverting input
pins. The frequency response is primarily determined by the
feedback resistor value as described previously. Increasing
its value will reduce the bandwidth, while decreasing it will
give a more peaked frequency response. The 499Ω feedback
resistor used in the typical performance specifications at a
gain of +2 on ±5V supplies is a good starting point for
design. Note that a 549Ω feedback resistor, rather than a
direct short, is recommended for the unity gain follower
application. A current feedback op amp requires a feedback
resistor even in the unity gain follower configuration to
control stability.
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OPA3681
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