ADS8422 Datasheet, PDF (20/25 Pages) Burr-Brown (TI) – 16-BIT, 4-MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE, REFERENCE

ADS8422
SLAS512B – JUNE 2006 – REVISED DECEMBER 2006
www.ti.com
PRINCIPLES OF OPERATION (continued)
Conversions are initiated by bringing the CONVST pin low for a minimum of 20 ns (after the 20 ns minimum
requirement has been met, the CONVST pin can be brought high). The converter switches from sample to hold
mode on the falling edge of the CONVST command. A clean and low jitter falling edge of this signal is important
to the performance of the converter. The BUSY pin is brought high immediately following CONVST going low.
BUSY stays high through the conversion process and returns low when the conversion has ended and data is
available on the DB pins. Once the conversion is started, it cannot be stopped except with an asynchronous
RESET (or a logical PD1).
If CONVST is detected high at the end of conversion, the device immediately enters sampling mode and the
analog input is connected to the CDAC. Otherwise, the CDAC is connected to the analog input only when
CONVST goes high. The high duration of CONVST should be at least 100 ns. There is no maximum high pulse
duration specification for CONVST.
Reading Data
The ADS8422 outputs full parallel data in 2’s complement format as shown in Table 1. The parallel output is
active when CS and RD are both low. There is a minimal quiet zone requirement around the falling edge of
CONVST. This is 30 ns prior to the falling edge of CONVST and 10 ns after the falling edge. No data read
should be attempted within this zone. Any other combination of CS and RD three-states the parallel output.
BYTE is used for multi-word read operation. BYTE is used whenever lower bits on the bus are output on the
higher byte of the bus. Refer to Table 1 for ideal output codes.
Table 1. Ideal Input Voltages and Output Codes
DESCRIPTION
Full scale range
Least significant bit (LSB)
+Full scale
Midscale
Midscale – 1 LSB
-Full scale
ANALOG VALUE
2V_ref
2V_ref)/65536
(+V_ref) –
0V
0V–
–V_ref+
DIGITAL OUTPUT 2'S COMPLIMENT
BINARY CODE
0111 1111 1111 1111
0000 0000 0000 0000
1111 1111 1111 1111
1000 0000 0000 0000
HEX CODE
7FFF
0000
FFFF
8000
The output data can be read as a full 16-bit word on pins DB15 – DB0 (MSB-LSB) if BYTE is low.
The result may also be read on an 8-bit bus for convenience. This is done by using only pins DB15-DB8. In this
case two reads are necessary: the first as before, leaving BYTE low and reading the 8 most significant bits on
pins DB15-DB8, then bringing BYTE high. When BYTE is high, the low bits (D7-D0) appear on pins DB15-DB8.
These multi-word read operations can be performed with a multiple active (toggling) RD signal or with the RD
signal tied low for simplicity.
BYTE
High
Low
Table 2. Conversion Data Read Out
PINS
DB15–DB8
D7 - D0
D15 - D8
DATA READ OUT
PINS
DB7–DB0
All One's
D7 - D0
RESET
RESET/PD1 is an asynchronous active low input signal. Maximum RESET/PD1 low time is 0.5 µs to avoid ADC
powerdown. Current conversion is aborted no later than 20 ns after the converter is in reset mode. The
converter returns to normal operation mode no later than 20 ns after the RESET/PD1 input is brought high (see
Figure 28).
The converter provides two power saving options: ADC powerdown (using pin 38, PD1) and analog output
powerdown (PD2).
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