ADS5240 Datasheet, PDF (20/24 Pages) Burr-Brown (TI) – 4-Channel, 12-Bit, 40MSPS ADC with Serial LVDS Interface

ADS5240
SBAS326C – JUNE 2004 – REVISED DECEMBER 2004
It is recommended that the isolation be maintained
onboard by using separate supplies to drive AVDD
and LVDD, as well as separate ground planes for
AVSS and LVSS.
The use of LVDS buffers reduces the injected noise
considerably, compared to CMOS buffers. The cur-
rent in the LVDS buffer is independent of the direction
of switching. Also, the low output swing as well as the
differential nature of the LVDS buffer results in
low-noise coupling.
POWER-DOWN MODE
The ADS5240 has a power-down pin, PD. Pulling PD
high causes the device to enter the power-down
mode. In this mode, the reference and clock circuitry
as well as all the channels are powered down. Device
power consumption drops to less than 100mW in this
mode. Individual channels can also be selectively
powered down by programming registers.
The ADS5240 also has an internal circuit that moni-
tors the state of stopped clocks. If ADCLK is stopped
(or if it runs at a speed < 3MHz), this monitoring
circuit generates a logic signal that puts the device in
a power-down state. As a result, the power consump-
tion of the device is reduced when ADCLK is
stopped. This circuit can also be disabled using
register options.
SUPPLY SEQUENCE
The following supply sequence is recommended for
powering up the device:
1. AVDD is powered up.
2. LVDD is powered up.
During the power-up ramp, the AVDD and LVDD
supplies should track each other to within 0.6V.
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If this sequencing is not possible, then it is rec-
ommended that AVDD and LVDD be powered up
simultaneously.
After the supplies have stabilized, it is required to
give the device an active RESET pulse. This results
in all internal registers getting reset to their default
value of 0 (inactive). Without RESET, it is possible
that some registers might be in their non-default state
on power-up. This could cause the device to
malfunction.
LAYOUT OF PCB WITH PowerPAD
THERMALLY-ENHANCED PACKAGES
The ADS5240 is housed in an 64-lead PowerPAD
thermally-enhanced package. To make optimum use
of the thermal efficiencies designed into the
PowerPAD package, the printed circuit board (PCB)
must be designed with this technology in mind.
Please refer to PowerPAD brief SLMA004 PowerPAD
Made Easy (refer to our web site at www.ti.com),
which addresses the specific considerations required
when integrating a PowerPAD package into a PCB
design. For more detailed information, including ther-
mal modeling and repair procedures, please see
technical brief SLMA002, PowerPAD Ther-
mally-Enhanced Package (available for download at
www.ti.com).
CONNECTING HIGH-SPEED,
MULTI-CHANNEL ADCs TO XILINX FPGAs
A separate application note (XAPP774) describing
how to connect TI's high-speed, multi-channel ADCs
with serial LVDS outputs to XILINX FPGAs can be
downloaded directly from the XILINX website
(http://www.xilinx.com).
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