VCA2612 Datasheet, PDF (19/19 Pages) Burr-Brown (TI) – TMDual, VARIABLE GAIN AMPLIFIER with Low Noise Preamp

PGA POST-AMPLIFIER—DETAIL
Figure 14 shows a simplified circuit diagram of the PGA
block. As described previously, the PGA gain is programmed
with the same MGS bits which control the VCA maximum
attenuation factor. Specifically, the PGA gain at each MGS
setting is the inverse (reciprocal) of the maximum VCA
attenuation at that setting. Therefore, the VCA • PGA
overall gain will always be 0dB (unity) when the analog
VCA_CNTL input is set to 0V (= maximum attenuation). For
VCA_CNTL = 3V (no attenuation), the VCA • PGA gain will
be controlled by the programmed PGA gain (24 to 45 dB in
3dB steps).
For clarity, the gain and attenuation factors are detailed in
Table III.
MGS VCA GAIN min to max
SETTING VCA_CNTL = 0V to 3V
000
–24dB to 0dB
001
–27dB to 0dB
010
–30dB to 0dB
011
–33dB to 0dB
100
–36dB to 0dB
101
–39dB to 0dB
110
–42dB to 0dB
101
–45dB to 0dB
DIFFERENTIAL
PGA GAIN
24dB
27dB
30dB
33dB
36dB
39dB
42dB
45dB
VCA • PGA GAIN
min to max
0dB to 24dB
0dB to 27dB
0dB to 30dB
0dB to 33dB
0dB to 36dB
0dB to 39dB
0dB to 42dB
0dB to 45dB
TABLE III. MGS Settings.
The PGA architecture consists of a differential, program-
mable-gain voltage to current converter stage followed by
transimpedance amplifiers to create and buffer each side of
the differential output. The circuitry associated with the
voltage to current converter is similar to that previously
described for the LNP, with the addition of eight selectable
PGA gain-setting resistor combinations (controlled by the
MGS bits) in place of the fixed resistor network used in the
LNP. Low input noise is also a requirement of the PGA
design due to the large amount of signal attenuation which
can be inserted between the LNP and the PGA. At minimum
VCA attenuation (used for small input signals) the LNP
noise dominates; at maximum VCA attenuation (large input
signals) the PGA noise dominates. Note that if the PGA
output is used single-ended, the apparent gain will be 6dB
lower.
+Out
R_L
Q₁
Q₁₁
V_DD
To Bias
Circuitry
Q₁₂
Q₉
R_L
V_CM
Q₃
R_S1
Q₁₃
Q₈
V_CM
R_S2
+In
Q₄
Q₇
–In
Q₁₄
Q₂
Q₁₀
Q₅
Q₆
To Bias
Circuitry
–Out
FIGURE 14. Simplified Block Diagram of the PGA.
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VCA2612