OPA2681 Datasheet, PDF (19/21 Pages) Burr-Brown (TI) – Dual Wideband, Current Feedback OPERATIONAL AMPLIFIER With Disable

DISABLE OPERATION (SO-14 ONLY)
The OPA2681N provides an optional disable feature that
may be used either to reduce system power or to implement
a simple channel multiplexing operation. If the DIS control
pin is left unconnected, the OPA2681N will operate nor-
mally. To disable, the control pin must be asserted low.
Figure 11 shows a simplified internal circuit for the disable
control feature.
+V_S
The transition edge rate (dv/dt) of the DIS control line will
influence this glitch. For the plot of Figure 12, the edge rate
was reduced until no further reduction in glitch amplitude
was observed. This approximately 1V/ns maximum slew
rate may be achieved by adding a simple RC filter into the
V_DIS pin from a higher speed logic line. If extremely fast
transition logic is used, a 2kΩ series resistor between the
logic gate and the V_DIS input pin will provide adequate
bandlimiting using just the parasitic input capacitance on the
V_DIS pin while still ensuring adequate logic level swing.
15kΩ
Q1
40
Output Voltage
20
(0V Input)
0
–20
–40
V_DIS
4.8V
25kΩ
110kΩ
V_DIS
I_S
Control
–V_S
0.2V
Time (20ns/div)
FIGURE 11. Simplified Disable Control Circuit, Each
Channel.
FIGURE 12. Disable/Enable Glitch.
THERMAL ANALYSIS
In normal operation, base current to Q1 is provided through
the 110kΩ resistor while the emitter current through the
15kΩ resistor sets up a voltage drop that is inadequate to
turn on the two diodes in Q1’s emitter. As V_DIS is pulled
low, additional current is pulled through the 15kΩ resistor
eventually turning on these two diodes (≈ 100uA). At this
point, any further current pulled out of V_DIS goes through
those diodes holding the emitter-base voltage of Q1 at
approximately zero volts. This shuts off the collector current
out of Q1, turning the amplifier off. The supply current in
the disable mode are only those required to operate the
circuit of Figure 11. Additional circuitry ensures that turn-on
time occurs faster than turn-off time (make-before-break).
When disabled, the output and input nodes go to a high
impedance state. If the OPA2681 is operating in a gain of
+1, this will show a very high impedance (4pF || 1MΩ) at the
output and exceptional signal isolation. If operating at a
gain greater than +1, the total feedback network resistance
(R_F + R_G) will appear as the impedance looking back into the
output, but the circuit will still show very high forward and
reverse isolation. If configured as an inverting amplifier, the
Due to the high output power capability of the OPA2681,
heatsinking or forced airflow may be required under extreme
operating conditions. Maximum desired junction tempera-
ture will set the maximum allowed internal power dissipa-
tion as described below. In no case should the maximum
junction temperature be allowed to exceed 175°C. Operating
junction temperature (T_J) is given by T_A + P_D • θ_JA. The total
internal power dissipation (P_D) is the sum of quiescent
power (P_DQ) and additional power dissipation in the output
stage (P_DL) to deliver load power. Quiescent power is simply
the specified no-load supply current times the total supply
voltage across the part. P_DL will depend on the required
output signal and load but would, for a grounded resistive
load, be at a maximum when the output is fixed at a voltage
equal to 1/2 of either supply voltage (for equal bipolar
supplies). Under this condition, P_DL = V_S2/(4 • R_L) where R_L
includes feedback network loading.
Note that it is the power in the output stage and not into the
load that determines internal power dissipation.
As a worst-case example, compute the maximum T_J using an
OPA2681 SO-8 in the circuit of Figure 1 operating at the
input and output will be connected through the feedback maximum specified ambient temperature of +85°C with
network resistance (R_F + R_G) giving relatively poor input to
output isolation.
One key parameter in disable operation is the output glitch
when switching in and out of the disabled mode. Figure 12
shows these glitches for the circuit of Figure 1 with the input
signal set to zero volts. The glitch waveform at the output
pin is plotted along with the DIS pin voltage.
both outputs driving a grounded 20Ω load to +2.5V.
P_D = 10V • 14.4mA + 2 • [52/(4 • (20Ω || 804Ω))] = 785mW
Maximum T_J = +85°C + (0.79 • 125°C/W) = 184°C
This absolute worst case condition exceeds specified maxi-
mum junction temperature. Normally this extreme case will
not be encountered. Careful attention to internal power
dissipation is required.
®
19
OPA2681