CS4297 Datasheet, PDF (19/46 Pages) Cirrus Logic – CrystalClear SoundFusion Audio Codec 97

CS4297
CrystalClear™ SoundFusion™ Audio Codec ’97
Slot 1: Read-Back Address Port
Slot 1 is the Read-Back Address Port. The Read-Back Address Port is used to echo the AC’97 Register
address back to the AC’97 Controller when the CS4297 has been issued a read request from the previous
frame. Included only for historical purposes, this address may be used by the AC’97 Controller to synchro-
nize read accesses. The CS4297 will only echo the register index for a read access. Write accesses will not
return valid data in Slot 1. The 20 bits of this slot are defined as:
F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35
Bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 RI6 RI5 RI4 RI3 RI2 RI1 RI0 0 0 0 0 0 0 0 0 0 0 0 0
RI6 - RI0 - Bits 18-12 contain the 7-bit register index to the AC’97 Registers in the CS4297.
All other undefined bits in Slot 1 will be returned by the CS4297 ‘cleared’.
Slot 2: Read-Back Data Port
Slot 2 is the Read-Back Data Port. The Read-Back Data Port contains the register data requested by the
AC’97 Controller from the previous read request. It reflects the valid data bits from the 16-bit AC’97 Reg-
ister being read. All read requests will return read addresses and data on the following serial data frame.
The 20 bits of this slot are defined as:
F36 F37 F38 F39 F40 F41 F42 F43 F44 F45 F46 F47 F48 F49 F50 F51 F52 F53 F54 F55
Bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 0 0 0 0
WD15 - WD0 - Bits 19-4 contain the 16-bit AC’97 Register value returned to the AC’97 Controller by the
CS4297. Bits 3-0 are undefined in Slot 2 and will be returned by the CS4297 ‘cleared’.
NOTE: The CS4297 implements bus-keeper logic for its 16-bit registers. Any read accesses from AC’97
Registers with undefined bits may return a ‘set’ or ‘clear’ value. The value returned depends on the state
of that bit location from the previous access. No AC’97 Controller software dependencies should exist on
the value of undefined AC’97 Register bits. For a list of the undefined bits in the AC’97 register map, see
Table 2, Mixer Registers.
Slot 3: Left Channel PCM Capture Data
Slot 3 contains the left channel data. The 20 bits of this slot are defined as:
F56 F57 F58 F59 F60 F61 F62 F63 F64 F65 F66 F67 F68 F69 F70 F71 F72 F73 F74 F75
Bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LP17 LP16 LP15 LP14 LP13 LP12 LP11 LP10 LP9 LP8 LP7 LP6 LP5 LP4 LP3 LP2 LP1 LP0 0 0
LP17 - LP0 - This is the 18-bit PCM 2’s compliment capture data from the left channel ADC in the
CS4297. The PCM capture data is left justified in the most significant 18 of the 20 bits in the slot.
The least significant 2 bits will be ‘cleared’.
DS242F5
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