ADS8472 Datasheet, PDF (19/30 Pages) Burr-Brown (TI) – 16-BIT, 1-MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE, REFERENCE

ADS8472
www.ti.com
APPLICATION INFORMATION
SLAS514 – DECEMBER 2006
ADS8472 TO A HIGH PERFORMANCE DSP INTERFACE
Figure 37 shows a parallel interface between the ADS8472 and a Texas instruments high performance DSP
such as the TMS320C6713 using the full 16-bit bus. The ADS8472 is mapped onto the CE2 memory space of
the TMS320C6713 DSP. The read and reset signals are generated by using a 3-to-8 decoder. A read operation
from the address 0xA000C000 generates a pulse on the RD pin of the data converter, wheras a read operation
form word address 0xA0014000 generates a pulse on the RESET/PD1 pin. The CE2 signal of the DSP acts as
CS (chip select) for the converter. As the TMS320C6713 features a 32-bit external memory interface, the BYTE
input of the converter can be tied permanently low, disabling the foldback of the data bus. The BUSY signal of
the ADS8472 is appiled to the EXT_INT6 interrupt input of the DSP, enabling the EDMA controller to react on
the falling edge of this signal and to collect the conversion result. The TOUT1 (timer out 1) pin of the
TMS320C6713 is used to source the CONVST signal of the converter.
+VA = 5 V
0.1 mF
AGND
10 mF
1 mF
CE2
CS
TMS320C6713
DSP
EA[16:14]
ARE
TOUT1
EXT_INT6
ED[15:0]
Address
Decoder
RD
ADS8472 +VBD
CONVST
BUSY
DB[15:0]
BDGND
BYTE
Figure 37. ADS8472 Application Circuitry
Analog 5 V
Ext Ref
Input
Analog
Input
I/O Supply
+VBD +2.7 V
0.1 mF
I/O Digital Ground
BDGND
0.1 µF
10 µF
AGND
0.1 µF
1 µF
AGND
ADS8472
Figure 38. ADS8472 Using Internal Reference
Submit Documentation Feedback
19