OPA2682 Datasheet, PDF (18/19 Pages) Burr-Brown (TI) – Dual, Wideband, Fixed Gain BUFFER AMPLIFIER With Disable

mately zero volts. This shuts off the collector current out of
Q1, turning the amplifier off. The supply current in the
disable mode is only that required to operate the circuit of
Figure 7. Additional circuitry ensures that turn-on time
occurs faster than turn-off time (make-before-break).
When disabled, the output and input nodes go to a high
impedance state. If the OPA2682N is operating in a gain of
+1, this will show a very high impedance (4pF || 1MΩ) at the
output and exceptional signal isolation. If operating at a gain
of +2, the total feedback network resistance (R_F + R_G) will
appear as the impedance looking back into the output, but
the circuit will still show very high forward and reverse
isolation. If configured as at a gain of –1, the input and
output will be connected through the feedback network
resistance (R_F + R_G) giving relatively poor input to output
isolation.
One key parameter in disable operation is the output glitch
when switching in and out of the disabled mode. Figure 8
shows these glitches for the circuit of Figure 1 with the input
signal set to zero volts. The glitch waveform at the output
pin is plotted along with the DIS pin voltage.
40
Output Voltage
20
(0V Input)
0
–20
–40
V_DIS
4.8V
0.2V
Time (20ns/div)
FIGURE 8. Disable/Enable Glitch.
The transition edge rate (dV/dt) of the DIS control line will
influence this glitch. For the plot of Figure 8, the edge rate
was reduced until no further reduction in glitch amplitude
was observed. This approximately 1V/ns maximum slew
rate may be achieved by adding a simple RC filter into the
V_DIS pin from a higher speed logic line. If extremely fast
transition logic is used, a 2kΩ series resistor between the
logic gate and the DIS input pin will provide adequate
bandlimiting using just the parasitic input capacitance on the
DIS pin while still ensuring an adequate logic level swing.
THERMAL ANALYSIS
Due to the high output power capability of the OPA2682,
heatsinking or forced airflow may be required under extreme
operating conditions. Maximum desired junction tempera-
ture will set the maximum allowed internal power dissipa-
tion as described below. In no case should the maximum
junction temperature be allowed to exceed 175°C.
Operating junction temperature (T_J) is given by T_A + P_D • θ_JA.
The total internal power dissipation (P_D) is the sum of
quiescent power (P_DQ) and additional power dissipated in the
output stage (P_DL) to deliver load power. Quiescent power is
simply the specified no-load supply current times the total
supply voltage across the part. P_DL will depend on the
required output signal and load but would, for a grounded
resistive load, be at a maximum when the output is fixed at a
voltage equal to 1/2 either supply voltage (for equal bipolar
supplies). Under this condition PDL = V_S2/(4 • R_L) where R_L
includes feedback network loading.
Note that it is the power in the output stage and not in the
load that determines internal power dissipation.
As a worst-case example, compute the maximum T_J using an
OPA2682U (SO-8 package) in the circuit of Figure 1 oper-
ating at the maximum specified ambient temperature of
+85°C with both outputs driving a grounded 100Ω load to
+2.5V:
P_D = 10V • 13.2mA + 2 [5²/(4 • (20Ω || 800Ω)) = 273mW
Maximum T_J = +85°C + (0.27W • 125°C/W) = 119°C
This worst-case condition is still well within rated maximum
T_J for this 100Ω load. Heavier loads may, however, exceed
the 175°C maximum junction temperature rating. Careful
attention to internal power dissipation is required, and forced
air cooling may be required.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high frequency
amplifier like the OPA2682 requires careful attention to
board layout parasitics and external component types. Rec-
ommendations that will optimize performance include:
a) Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the
output pin can cause instability; on the non-inverting input,
it can react with the source impedance to cause unintentional
bandlimiting. To reduce unwanted capacitance, a window
around the signal I/O pins should be opened in all of the
ground and power planes around those pins. Otherwise,
ground and power planes should be unbroken elsewhere on
the board.
b) Minimize the distance (< 0.25") from the power sup-
ply pins to high frequency 0.1µF decoupling capacitors.
At the device pins, the ground and power plane layout
should not be in close proximity to the signal I/O pins. Avoid
narrow power and ground traces to minimize inductance
between the pins and the decoupling capacitors. The power
supply connections (on pins 4 and 7) should always be
decoupled with these capacitors. An optional supply
decoupling capacitor across the two power supplies (for
bipolar operation) will improve 2nd harmonic distortion
performance. Larger (2.2µF to 6.8µF) decoupling capaci-
tors, effective at lower frequency, should also be used on the
main supply pins. These may be placed somewhat farther
from the device and may be shared among several devices in
the same area of the PC board.
®
OPA2682
18