CS4344 Datasheet, PDF (17/23 Pages) Cirrus Logic – 10-PIN, 24-BIT, 192KHz STEREO D/A CONVERTER

CS4344/5/6/8
When changing clock ratio or sample rate it is recommended that zero data (or near zero data) be present
on SDIN for at least 10 LRCK samples before the change is made. During the clocking change the DAC
outputs will always be in a zero data state. If no zero audio is present at the time of switching, a slight click
or pop may be heard as the DAC output automatically goes to it’s zero data state.
4.6 Grounding and Power Supply Decoupling
As with any high resolution converter, the CS4344 family requires careful attention to power supply and
grounding arrangements to optimize performance. Figure 6 shows the recommended power arrangement
with VA connected to a clean +3.3 V or +5 V supply. For best performance, decoupling and filter capaci-
tors should be located as close to the device package as possible with the smallest capacitors closest.
4.7 Analog Output and Filtering
The analog filter present in the CS4344 family is a switched-capacitor filter followed by a continuous time
low pass filter. Its response, combined with that of the digital interpolator, is given in Figures 13 - 20. The
recommended external analog circuitry is shown in the “Typical Connection Diagram” on page 11.
DS613PP2
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