PCM3501 Datasheet, PDF (16/24 Pages) Burr-Brown (TI) – Low Voltage, Low Power, 16-Bit, Mono VOICE/MODEM CODEC

SYNCHRONIZATION REQUIREMENTS
The PCM3501 requires that FS and BCK be synchronous
with the system clock. Internal circuitry is included to detect
a loss of synchronization between FS and the system clock
input. If the phase relationship between FS and the system
clock varies more than ± 1.5 BCK periods, the PCM3501
will detect a loss of synchronization. Upon detection, the
DAC output is forced to 0.5V_CC and the DOUT pin is forced
to a high impedance state. This occurs within one sampling
clock (FS) period of initial detection. Figure 10 shows the
loss of synchronization operation and the DAC and ADC
output delays associated with it.
TIME SLOT OPERATION
The PCM3501 serial interface supports Time Division
Multiplexing (TDM) using the Time Slot Mode. Up to four
PCM3501s may be connected on the same 4-wire serial
interface bus. This is useful for system applications that
require multiple modem or voice channels. Figure 11 shows
examples of Time Slot Mode connections.
Time Slot Mode defines a 64-bit long frame, composed of
four time slots. Each slot is 16 bits long and corresponds to
one of four CODECs. The FS pin on the first PCM3501
(CODEC A, Slot 0) is used as the master frame sync, and
operates at the sampling frequency, f_S. The bit clock, BCK,
operates at 64f_S. DIN and DOUT of each CODEC also
operate at 64f_S. Figure 12 shows the operation of the Time
Slot Mode.
Time Slot operation is enabled or disabled using the TSC
input (pin 7). The state of the TSC pin is updated at power-
on reset, or on the rising edge of PWDN input (if using
external reset or power-down mode). A forced reset is
required when changing from Slave to Master Mode, or visa
versa, in real time.
Synchronization
Lost
Resynchronization
State of
Synchronization
DAC V_OUT
Synchronous
Asynchronous
within
1/f_S
Undefined Data
Normal
V_COM
(0.5 V_CC)
Synchronous
t_DACDLY2 (32/f_S)
V_COM
(0.5 V_CC)
Normal
ADC DOUT
Undefined Data
Normal
High Impedance
t_ADCDLY2 (32/f_S)
Normal⁽¹⁾
NOTE: (1) The HPF transient response (exponentially attenuated signal from ±0.2% DC of FSR
with 200ms time constant) appears initially.
FIGURE 10. Loss of Synchronization Operation and Timing.
Controller
PCM3501
(CODEC A, Slot 0)
FS
BCK
DIN
DOUT
FSO
SCKIO
XTI
XTO
M/S
V_DD
TSC
V_DD
PCM3501
(CODEC B, Slot 1)
FS
BCK
DIN
DOUT
FSO
SCKIO
XTI
XTO
M/S
TSC
GND
V_DD
To Two PCM3500s
FIGURE 11. Time Slot Mode Connections.
®
PCM3501
16