PCM1796_06 Datasheet, PDF (16/60 Pages) Burr-Brown (TI) – 24-BIT, 192-kHz SAMPLING, ADVANCED SEGMENT, AUDIO STEREO DIGITAL-TO-ANALOG CONVERTER

PCM1796
SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006
www.ti.com
AUDIO DATA INTERFACE
Audio Serial Interface
The audio interface port is a 3-wire serial port. It includes LRCK (pin 4), BCK (pin 6), and DATA (pin 5). BCK is the
serial audio bit clock, and it is used to clock the serial data present on DATA into the serial shift register of the audio
interface. Serial data is clocked into the PCM1796 on the rising edge of BCK. LRCK is the serial audio left/right word
clock.
The PCM1796 requires the synchronization of LRCK and system clock, but does not need a specific phase relation
between LRCK and system clock.
If the relationship between LRCK and system clock changes more than ±6 BCK, internal operation is initialized within
1/f_S and analog outputs are forced to the bipolar zero level until resynchronization between LRCK and system clock
is completed.
PCM Audio Data Formats and Timing
The PCM1796 supports industry-standard audio data formats, including standard right-justified, I²S, and
left-justified. The data formats are shown in Figure 27. Data formats are selected using the format bits, FMT[2:0],
in control register 18. The default data format is 24-bit I²S. All formats require binary 2s complement, MSB-first audio
data. Figure 26 shows a detailed timing diagram for the serial audio interface.
LRCK
BCK
DATA
t(BCH)
t(BCL)
t(BCY)
t(BL)
t(LB)
t(DS)
t(DH)
t(BCY)
t(BCL)
t(BCH)
t(BL)
t(LB)
t(DS)
t(DH)
—
PARAMETERS
BCK pulse cycle time
BCK pulse duration, LOW
BCK pulse duration, HIGH
BCK rising edge to LRCK edge
LRCK edge to BCK rising edge
DATA setup time
DATA hold time
LRCK clock data
MIN MAX UNITS
70
ns
30
ns
30
ns
10
ns
10
ns
10
ns
10
ns
50% ± 2 bit clocks
Figure 26. Timing of Audio Interface
1.4 V
1.4 V
1.4 V
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