PCM1792A Datasheet, PDF (15/59 Pages) Burr-Brown (TI) – 24-bit,192-khz sampling,advanced segment, audio stereo digital-to-analog converter

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SYSTEM CLOCK AND RESET FUNCTIONS
PCM1792A
SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006
System Clock Input
The PCM1792A requires a system clock for operating the digital interpolation filters and advanced segment DAC
modulators. The system clock is applied at the SCK input (pin 7). The PCM1792A has a system clock detection circuit that
automatically senses if the system clock is operating between 128 f_S and 768 f_S. Table 1 shows examples of system clock
frequencies for common audio sampling rates. If the oversampling rate of the delta-sigma modulator is selected as 128 f_S,
the system clock frequency is over 256 f_S.
Figure 24 shows the timing requirements for the system clock input. For optimal performance, it is important to use a clock
source with low phase jitter and noise. One of the Texas Instruments’ PLL1700 family of multiclock generators is an
excellent choice for providing the PCM1792A system clock.
Table 1. System Clock Rates for Common Audio Sampling Frequencies
SAMPLING FREQUENCY
32 kHz
128 fS
4.096(1)
SYSTEM CLOCK FREQUENCY (fSCK) (MHz)
192 fS
6.144(1)
256 fS
8.192
384 fS
12.288
512 fS
16.384
44.1 kHz
5.6488(1)
8.4672
11.2896
16.9344
22.5792
48 kHz
6.144(1)
9.216
12.288
18.432
24.576
96 kHz
12.288
18.432
24.576
36.864
49.152(1)
192 kHz
24.576
36.864
49.152(1)
73.728(1)
(2)
(1) _{This system clock rate is not supported in I2C fast mode.}
(2) _{This system clock rate is not supported for the given sampling frequency.}
768 fS
24.576
33.8688
36.864
73.728(1)
(2)
H
System Clock (SCK)
L
t(SCKH)
t(SCKL)
t(SCY)
2V
0.8 V
PARAMETERS
t(SCY)
t(SCKH)
t(SCKL)
System clock pulse cycle time
System clock pulse duration, HIGH
System clock pulse duration, LOW
MIN
13
0.4t(SCY)
0.4t(SCY)
MAX
UNITS
ns
ns
ns
Figure 24. System Clock Input Timing
Power-On and External Reset Functions
The PCM1792A includes a power-on reset function. Figure 25 shows the operation of this function. With V_DD > 2 V, the
power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time V_DD > 2 V. After
the initialization period, the PCM1792A is set to its default reset state, as described in the MODE CONTROL REGISTERS
section of this data sheet.
The PCM1792A also includes an external reset capability using the RST input (pin 14). This allows an external controller
or master reset circuit to force the PCM1792A to initialize to its default reset state.
Figure 26 shows the external reset operation and timing. The RST pin is set to logic 0 for a minimum of 20 ns. The RST
pin is then set to a logic 1 state, thus starting the initialization sequence, which requires 1024 system clock periods. The
external reset is especially useful in applications where there is a delay between the PCM1792A power up and system clock
activation.
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