CS5516 Datasheet, PDF (15/41 Pages) Cirrus Logic – 16BIT/20-BIT BRIDGE TRANSDUCER A/D CONVERTER

CS5516, CS5520
Configuration Register
EC
CC3
CC2
CC1
CC0
1
1
0
0
0
1
0
1
0
0
1
0
0
1
0
1
0
0
0
1
1
1
1
0
0
0
X
X
X
X
CAL Type
VREF Non-ratiometric Offset
AIN Non-ratiometric Offset
AIN Ratiometric Offset
AIN System Gain
VREF & AIN Non-ratiometric Offset
End Calibration
Calibration Time
573,440/fclk
573,440/fclk
2,211,840/fclk
573,440/fclk
573,440/fclk
-
DRDY remains high through calibration sequence. In all modes, DRDY falls immediately upon completion of the calibration
sequence.
Table 3. CS5516/CS5520 Calibration Control
which calibration is initiated is common to each formed. The calibration steps should be per-
of the calibration registers. The configuration formed in the following sequence. If the user
register controls the execution of the calibration determines that non-ratiometric offset calibra-
process. Bits CC3--CC0 in the configuration tion is important, the non-ratiometric offset
register determine which type of calibration will errors of the VREF and AIN input channels
be performed and which of the five calibration should be calibrated first. Then the ratiometric
registers will be affected. On the falling edge of offset of the AIN channel should be calibrated.
the 24th SCLK, the configuration word will be And finally, the AIN channel gain should be
latched into the configuration register and the se- calibrated.
lected calibration will be executed. The time
required to perform a calibration is listed in Ta- Non-ratiometric Errors
ble 3. The DRDY pin will remain a logic 1
during calibration, and will go low when the
calibration step is completed.
To calibrate out the VREF and AIN
non-ratiometric errors, the input channels to the
VREF path into the converter and the AIN path
The serial port should not be accessed while a
calibration is in progress. The EC bit of the
configuration register remains a logic 1 until it is
overwritten by a new configuration word (EC =
0). Consequently, if EC is left active, any write
(the falling edge of the 24th SCLK) to any regis-
ter inside the converter will cause a re-execution
of the calibration sequence. This occurs because
into the converter must be grounded (this may
occur at the pins of the IC, or at the bridge exci-
tation as shown in Figure 3.). Then the EC,
CC2 and CC3 bits of the configuration register
must be set to logic 1. The converter will then
perform a non-ratiometric calibration and place
BX1
BX2
the internal microcontroller executes the contents
of the configuration register every time the 24th
CS5516
1B*
1A*
CS5520
SCLK falls after writing a 24-bit word to any
VREF+
internal register. To be certain that calibrations
VREF-
will not be re-executed each time a new word is
AIN+
written or read via the serial port, the EC bit of
the configuration register must be written back
+
-
to a logic 0 after the final calibration step has
been completed.
The CC3--CC0 bits of the configuration register
determine the type of calibration to be per-
AIN-
*Note: The bridge can be grounded with a
relay or with jumpers to perform
non-ratiometric calibration.
Figure 3. Non-ratiometric System Calibration using
Internal Excitation
DS74F21
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