CS4202 Datasheet, PDF (15/68 Pages) Cirrus Logic – Audio Codec 97 with headphone Amplifier

CS4202
3. AC-LINK FRAME DEFINITION
The AC-link is a bi-directional serial port with data
organized into frames consisting of one 16-bit and
twelve 20-bit time-division multiplexed slots.
Slot 0 is a special reserved time slot containing
16-bits which are used for AC-link protocol infra-
structure. Slots 1 through 12 contain audio or con-
trol/status data. Both the serial data output and
input frames are defined from the controller per-
spective, not from the CS4202 perspective.
The controller synchronizes the beginning of a
frame with the assertion of the SYNC signal.
Figure 9 shows the position of each bit location
within the frame. The first bit position in a new se-
rial data frame is F0 and the last bit position in the
serial data frame is F255. When SYNC goes active
(high) and is sampled active by the CS4202 (on the
falling edge of BIT_CLK), both devices are syn-
chronized to a new serial data frame. The data on
the SDATA_OUT pin at this clock edge is the final
bit of the previous frame’s serial data. On the next
rising edge of BIT_CLK, the first bit of Slot 0 is
driven by the controller on the SDATA_OUT pin.
On the next falling edge of BIT_CLK, the CS4202
latches this data in as the first bit of the frame.
Tag Phase
SYNC
BIT_CLK
12.288 MHz
81.4 ns
20.8 µ s
(48 kHz)
Data Phase
Bit Frame Position: F255
F0
F1
F2
F12
F13
F14 F15
F16
F35
F36
F56
F57
F76
F96
F255
SDATA_OUT
0
Valid Slot 1 Slot 2
Frame Valid Valid
Slot 12
Valid
0
Codec Codec
ID1
ID0
R/W
0 WD15
D19 D18
D19
D19
0
Bit Frame Position:
SDATA_IN
F255
GPIO
INT
F0
Codec
Ready
F1
Slot 1
Valid
F2
Slot 2
Valid
F12
F13
F14 F15
F16
Slot 12
Valid
0
0
0
0
F35
F36
F56 F57
F76
F96
F255
0 RD15
D19 D18
D19
D19
GPIO
INT
Slot 0
Slot 1
Slot 2
Slot 3
Figure 9. AC-link Input and Output Framing
Slot 4
Slots 5-12
DS549PP1
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