OPA2652 Datasheet, PDF (14/15 Pages) Burr-Brown (TI) – Dual, 700MHz, Voltage-Feedback OPERATIONAL AMPLIFIER

circuit. Most of these techniques add a DC current through
the feedback resistor. In selecting an offset trim method, one
key consideration is the impact on the desired signal path
frequency response. If the signal path is intended to be non-
inverting, the offset control is best applied as an inverting
summing signal to avoid interaction with the signal source.
If the signal path is intended to be inverting, applying the
offset control to the non-inverting input may be considered.
However, the DC offset voltage on the summing junction
will set up a DC current back into the source which must be
considered. Applying an offset adjustment to the inverting
op amp input can change the noise gain and frequency
response flatness. For a DC-coupled inverting amplifier,
Figure 9 shows one example of an offset adjustment tech-
nique that has minimal impact on the signal frequency
response. In this case, the DC offset current is brought into
the inverting input node through resistor values that are
much larger than the signal path resistors. This will insure
that the adjustment circuit has minimal effect on the loop
gain and hence the frequency response.
0.1µF
328Ω
+5V
Supply Decoupling
Not Shown
1/2
OPA2652
V_O
+5V
5kΩ
10kΩ
5kΩ
R_G
500Ω
V_I
20kΩ
0.1µF
–5V
–5V
R_F
1kΩ
±200mV Output Adjustment
V_{O = –} R_{F = –2}
V_I
R_G
FIGURE 9. DC-Coupled, Inverting Gain of –2, with Offset
Adjustment.
THERMAL ANALYSIS
Heatsinking or forced airflow may be required under ex-
treme operating conditions. Maximum desired junction tem-
perature will set the maximum allowed internal power dis-
sipation as described below. In no case should the maximum
junction temperature be allowed to exceed 175°C.
Operating junction temperature (T_J) is given by T_A + P_D•θ_JA.
The total internal power dissipation (P_D) is the sum of
quiescent power (P_DQ) and additional power dissipated in
the output stage (P_DL) to deliver load power. Quiescent
power is simply the specified no-load supply current times
the total supply voltage across the part. P_DL will depend on
the required output signal and load but would, for a grounded
resistive load, be at a maximum when the output is fixed at
a voltage equal to 1/2 of either supply voltage (for equal
bipolar supplies). Under this condition, P_DL = V_S2/(4•R_L)
where R_L includes feedback network loading.
Note that it is the power in the output stage, and not into the
load, that determines internal power dissipation.
As an example, compute the maximum T_J using an
OPA2652E (SOT23-8 package) in the circuit of Figure 1
operating at the maximum specified ambient temperature of
+85°C and with both outputs driving 2.5V_DC into a grounded
100Ω load.
P_D = 10V • 15.5mA + 2 [5²/(4•(100Ω || 804Ω))] = 296mW
Maximum T_J = +85°C + (0.30W • 150°C/W) = 130°C.
This absolute worst-case condition meets the specified maxi-
mum junction temperature. Actual P_DL will almost always
be less than that considered here. Carefully consider maxi-
mum T_J in your application.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high frequency
amplifier like the OPA2652 requires careful attention to
board layout parasitics and external component types. Rec-
ommendations that will optimize performance include:
a) Minimize parasitic capacitance to any AC ground for all
of the signal I/O pins. Parasitic capacitance on the output
and inverting input pins can cause instability: on the non-
inverting input, it can react with the source impedance to
cause unintentional bandlimiting. To reduce unwanted ca-
pacitance, a window around the signal I/O pins should be
opened in all of the ground and power planes around those
pins. Otherwise, ground and power planes should be unbro-
ken elsewhere on the board.
b) Minimize the distance (<0.25") from the power supply
pins to high frequency 0.1µF decoupling capacitors. At the
device pins, the ground and power plane layout should not
be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between
the pins and the decoupling capacitors. The power supply
connections should always be decoupled with these capaci-
tors. An optional supply decoupling capacitor (0.1µF) across
the two power supplies (for bipolar operation) will improve
2nd harmonic distortion performance. Larger (2.2µF to
6.8µF) decoupling capacitors, effective at lower frequency,
should also be used on the main supply pins. These may be
placed somewhat farther from the device and may be shared
among several devices in the same area of the PC board.
c) Careful selection and placement of external compo-
nents will preserve the high frequency performance of
the OPA2652. Resistors should be a very low reactance
type. Surface-mount resistors work best and allow a tighter
overall layout. Metal film or carbon composition axially-
leaded resistors can also provide good high frequency per-
formance. Again, keep their leads and PC board traces as
short as possible. Never use wirewound type resistors in a
high frequency application. Since the output pin and invert-
ing input pin are the most sensitive to parasitic capacitance,
always position the feedback and series output resistor, if
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OPA2652
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