INA203 Datasheet, PDF (14/25 Pages) Burr-Brown (TI) – Unidirectional Measurement Current-Shunt Monitor with Dual Comparators

INA203
INA204
INA205
SBOS393 – MARCH 2007
Note that the specified accuracy of the INA203,
INA204, and INA205 must then be combined in
addition to these tolerances. While this discussion
treated accuracy worst-case conditions by combining
the extremes of the resistor values, it is appropriate
to use geometric mean or root sum square
calculations to total the effects of accuracy
variations.
REFERENCE
The INA203, INA204, and INA205 include an internal
voltage reference that has a load regulation of
0.4mV/mA (typical), and not more than 100ppm/°C of
drift. Only the 14-pin package allows external access
to reference voltages, where voltages of 1.2V and
0.6V are both available. Output current versus output
voltage is illustrated in the Typical Characteristics
section.
COMPARATOR
The INA203, INA204, and INA205 devices
incorporate two open-drain comparators. These
comparators typically have 2mV of offset and a 1.3µs
(typical) response time. The output of Comparator 1
latches and is reset through the CMP1 RESET pin,
as shown in Figure 35. This configuration applies to
both the 10- and 14-pin versions. Figure 34
illustrates the comparator delay.
The 14-pin versions of the INA203, INA204, and
INA205 include additional features for comparator
functions. The comparator reference voltage of both
Comparator 1 and Comparator 2 can be overridden
by external inputs for increased design flexibility.
Comparator 2 has a programmable delay.
COMPARATOR DELAY (14-Pin Version Only)
The Comparator 2 programmable delay is controlled
by a capacitor connected to the CMP2 Delay Pin;
see Figure 30. The capacitor value (in µF) is
selected by using Equation 4:
C_DELAY (in mF) =
t_D
5
(4)
www.ti.com
A simplified version of the delay circuit for
Comparator 2 is shown in Figure 34. The delay
comparator consists of two comparator stages with
the delay between them. Note that I1 and I2 cannot
be turned on simultaneously; I1 corresponds to a U1
low output and I2 corresponds to a U1 high output.
Using an initial assumption that the U1 output is low,
I1 is on, then U2 +IN is zero. If U1 goes high, I2
supplies 120nA to C_DELAY. The voltage at U2 +IN
begins to ramp toward a 0.6V threshold. When the
voltage crosses this threshold, the U2 output goes
high while the voltage at U2 +IN continues to ramp
up to a maximum of 1.2V when given sufficient time
(twice the value of the delay specified for C_DELAY).
This entire sequence is reversed when the
comparator outputs go low, so that returning to low
exhibits the same delay.
1.2V
I2
120nA
U1
U2
I1
120nA
C_DELAY
0.6V
Figure 34. Simplified Model of the Comparator 2
Delay Circuit
0.6V
V_IN
0V
CMP Out
RESET
Figure 35. Comparator Latching Capability
14
Submit Documentation Feedback