CS8952 Datasheet, PDF (14/82 Pages) Cirrus Logic – CrystalLAN 100BASE-X and 10BASE-T Transceiver

CS8952
10BASE-T MII TRANSMIT TIMING
Parameter
Symbol
Min
Typ
Max
Unit
TXD[3:0] Setup to TX_CLK High
t_SU1
10
-
-
ns
TX_ER Setup to TX_CLK High
t_SU2
10
-
-
ns
TX_EN Setup to TX_CLK High
t_SU3
10
-
-
ns
TXD[3:0] Hold after TX_CLK High
t_HD1
0
-
-
ns
TX_ER Hold after TX_CLK High
t_HD2
0
-
-
ns
TX_EN Hold after TX_CLK High
t_HD3
0
-
-
ns
TX_EN “high” to CRS asserted latency
t_CRS1
0
-
4
BT
TX_EN “low” to CRS de-asserted latency
t_CRS2
0
-
16
BT
TX_EN “high” to TX+/- output (TX Latency)
t_LAT
6
-
14
BT
SQE Timing
COL (SQE) Delay after CRS de-asserted
COL (SQE) Pulse Duration
t_COL
0.65
0.9
t_COLP
0.65
1.0
1.6
µs
1.6
µs
TX_CLK
t_SU3
TX_EN
t_SU2
TX_ER
t_SU1
TXD[3:0]
CRS
TX+/-
10BASE-T Transmit Timing
t_HD3
t_HD2
t_HD1
t_CRS1
t_LAT
Valid
Data
TX_CLK
SQE Timing
COL
t_SQE
t_SQEP
t_CRS2
Input/Output
Input
Input
Input
Output
Output
Input/Output
Output
14
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver