DAC7617 Datasheet, PDF (11/14 Pages) Burr-Brown (TI) – Quad, Serial Input, 12-Bit, Voltage Output DIGITAL-TO-ANALOG CONVERTER

REFERENCE INPUTS
The minimum output of each DAC is equal to V_REFL plus
a small offset voltage (essentially, the offset of the output
op amp). The maximum output is equal to V_REFH – 1LSBplus
a similar offset voltage.
The current into the reference inputs depends on the DAC
output voltages and can vary from a few microamps to
approximately 0.4 milliamp. Bypassing the reference volt-
age or voltages with a 0.1µF capacitor placed as close as
possible to the DAC7617 package is strongly recommended.
DIGITAL INTERFACE
Figure 2 and Table I provide the basic timing for the
DAC7617. The interface consists of a serial clock (CLK),
serial data (SDI), a load register signal (LOADREG), and a
“load all DAC registers” signal (LDAC). In addition, a chip
select (CS) input is available to enable serial communication
when there are multiple serial devices. An asynchronous
reset input (RESET) is provided to simplify start-up condi-
tions, periodic resets, or emergency resets to a known state.
SYMBOL
DESCRIPTION
MIN TYP MAX UNITS
t_DS
Data Valid to CLK Rising
25
ns
t_DH
Data Held Valid after CLK Rises 20
ns
t_CH
CLK HIGH
30
ns
t_CL
CLK LOW
50
ns
t_CSS
CS LOW to CLK Rising
55
ns
t_CSH
CLK HIGH to CS Rising
15
ns
t_LD1
LOADREG HIGH to CLK Rising 40
ns
t_LD2
CLK Rising to LOADREG LOW 15
ns
t_LDRW
LOADREG LOW Time
45
ns
t_LDDW
LDAC LOW Time
45
ns
t_RSSH
RESETSEL Valid to RESET LOW 25
ns
t_RSTW
RESET LOW Time
70
ns
t_S
Settling Time
10
µs
TABLE I. Timing Specifications (T_A = –40°C to +85°C).
The DAC code and address are provided via a 16-bit serial
interface, as shown in Figure 2. The first two bits select the
input register that will be updated when LOADREG goes
LOW (see Table II). The next two bits are not used. The last
12 bits are the DAC code which is provided, most significant
bit first.
SDI
CLK
CS
LOADREG
SDI
CLK
LDAC
V_OUT
RESET
RESETSEL
A1 A0 X
(MSB)
X D11 D10 D9
(LSB)
D3 D2 D1 D0
tcss
t_LD1
t_DS
t_CL
t_DH
t_CH
t_CSH
t_LD2
t_LDRW
t_LDDW
t_S
1 LSB
ERROR BAND
t_RSSH
t_S
t_RSTW
1 LSB
ERROR BAND
FIGURE 2. DAC7617 Timing.
DAC7617
11
SBAS185