TSC2046E_07 Datasheet, PDF (10/30 Pages) Burr-Brown (TI) – Low Voltage I/O TOUCH SCREEN CONTROLLER

TSC2046E
SBAS417 − JUNE 2007
ANALOG INPUT
Figure 2 shows a block diagram of the input multiplexer on
the TSC2046E, the differential input of the ADC, and the
differential reference of the converter. Table 1 and Table 2
show the relationship between the A2, A1, A0, and
SER/DFR control bits and the configuration of the
TSC2046E. The control bits are provided serially via the DIN
pin—see the Digital Interface section of this data sheet for
more details.
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When the converter enters the hold mode, the voltage
difference between the +IN and –IN inputs (shown in
Figure 2) is captured on the internal capacitor array. The
input current into the analog inputs depends on the
conversion rate of the device. During the sample period, the
source must charge the internal sampling capacitor (typically
25pF). After the capacitor is fully charged, there is no further
input current. The rate of charge transfer from the analog
source to the converter is a function of conversion rate.
PENIRQ IOVDD
Level
Shifter
50kΩ
or
90kΩ
TEMP1
TEMP0
+V_CC
V_REF
Logic
A2− A0
(Shown 001_B)
SER/DFR
(Shown Low)
X+
X−
Y+
Y−
V_BAT
7.5kΩ
AUX
GND
2.5kΩ
Battery
On
2.5V
Reference
Ref On/Off
+REF
+IN
ADC
−IN
−REF
Figure 2. Simplified Diagram of Analog Input
A2 A1 A0 VBAT AUXIN
TEMP
Y− X+ Y+ Y-POSITION X-POSITION Z1-POSITION Z2-POSITION X-DRIVERS Y-DRIVERS
000
+IN (TEMP0)
Off
Off
001
+IN
Measure
Off
On
0 1 0 +IN
Off
Off
011
+IN
Measure
X−, On
Y+, On
100
+IN
Measure
X−, On
Y+, On
101
+IN
Measure
On
Off
110
+IN
Off
Off
111
+IN (TEMP1)
Off
Off
Table 1. Input Configuration (DIN), Single-Ended Reference Mode (SER/DFR high)
A2
A1
A0
+REF −REF Y−
X+
Y+
Y-POSITION X-POSITION Z1-POSITION Z2-POSITION DRIVERS
0
0
1
Y+
Y−
+IN
Measure
Y+, Y−
0
1
1
Y+
X−
+IN
Measure
Y+, X−
1
0
0
Y+
X−
+IN
Measure
Y+, X−
1
0
1
X+
X−
+IN
Measure
X+, X−
Table 2. Input Configuration (DIN), Differential Reference Mode (SER/DFR low)
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